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Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware. © 2010 IEEE.

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n,k) -adjacent bit pseudo-exhaustive test sets, all 2k binary combinations appear to all adjacent -bit groups of inputs.With recursive pseudoexhaustive generation, all (n,k) -adjacent bit pseudoexhaustive tests are generated for k ≤ n and more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern (n,k) -adjacent bit pseudoexhaustive tests for all k≤ n. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented. © 2009 IEEE.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing. © 2008 IEEE.

Built-in self test (BIST) techniques provide for on-chip test pattern generation and response verification operations, and therefore constitute an efficient alternative to external testing for the detection of faults appearing in VLSI circuits. Failure mechanisms that commonly appear in high-speed CMOS VLSI circuits cannot be modelled adequately as stuck-at faults. The detection of these faults requires the application of pairs of patterns to the inputs of the circuit under test. Single input change (SIC) pairs are pairs of patterns where the first pattern of each pair differs from the second pattern in exactly one bit. SIC pairs have been proved to be extremely useful for the detection of stuck-open and delay faults. In this paper a novel algorithm for the generation of SIC pairs is presented, termed decoder-based SIC pair generation (DSG) algorithm. An implementation of the DSG algorithm in a BIST environment is also presented. The number of memory elements utilised is the lowest reported in the literature. © The Institution of Engineering and Technology 2006.

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits. © 2005 IEEE.

Built-in Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed Concurrent Test Latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to Concurrent Test Latency and hardware overhead trade-off, for low values of the hardware overhead. © 2005 IEEE.

In this paper an algorithm for the generation of single input change (SIC) pairs is presented, termed the accumulator-based SIC pair generation (ASG) algorithm; SIC pairs have been effectively utilised for testing robustly detectable sequential faults. ASG is implemented in hardware utilising an accumulator whose inputs are driven by a barrel shifter. Since such structures (accumulators whose inputs are driven by barrel shifters) are commonly found in current, highspeed signal processing VLSI circuits, the presented schema provides a practical solution for the built-in testing of such circuits for testing delay and stuck-open faults. Utilisation of ASG to applying SIC pairs to adjacent pairs of inputs of the CUT, resulting in pseudoexhaustive schemes, is also addressed.

Two-pattern tests target the detection of most common failure mechanisms in CMOS VLSI circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2n×(2n-1)+1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into datapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmenting existing datapath components, rather than building a new pattern generation structure.

Single Input Change (SIG) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.