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Planar hypergraphs are widely used in several applications, including VLSI design, metro maps, information visualisation, and databases. The minimum s - t hypercut problem in a weighted hypergraph is to find a partition of the vertices into two nonempty sets, S and S ¯ , with s ∈ S and t ∈ S ¯ that minimizes the total weight of hyperedges that have at least two endpoints in two different sets. In the present study, we propose an approach that effectively solves the minimum s - t hypercut problem in (s, t)-planar hypergraphs. The method proposed demonstrates polynomial time complexity, providing a significant advancement in solving this problem. The modelling example shows that the proposed strategy is effective at obtaining balanced bipartitions in VLSI circuits. [ABSTRACT FROM AUTHOR]

Electronics industry has attained huge development in last few decades due to the rapid increase in system design applications. With the growth of very large scale integration (VLSI) design, integrated circuits (ICs) are employed in many applications. VLSI design comprises many steps like system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. HLS interprets behavior description and create digital hardware that executes the behavior. But, the power-process-voltage-temperature (PPVT) variation can causee many issues and reduce the performance of VLSI design circuits. In order to address these problems, Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for better runtime adaptability with minimal time consumption. VLSI circuits are designed with the behavioral input and the output performance is measured at runtime. The behavioral description of the circuit is taken as input. Then, source code compilation process translates high level specification into Intermediate Representation (IR) and converts to control/data flow graph (CDFG). CDFG reveals data and control dependencies between operations. The proposed Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for providing better runtime adaptability with minimal time consumption. Finally, Register Transfer Level Generation is carried out to yield better runtime adaptability with minimal time. Simulation results on ISCAS'89 Benchmark Dataset, shows that the RDNLC-HLS model increases the FUSA with minimal error rate and CAT. [ABSTRACT FROM AUTHOR]

Discrete two-dimensional orthogonal wavelet transforms find applications in many areas of analysis and processing of digital images. In a typical scenario the separability of two-dimensional wavelet transforms is assumed and all calculations follow the row-column approach using one-dimensional transforms. For the calculation of one-dimensional transforms the lattice structures, which can be characterized by high computational efficiency and non-redundant parametrization, are often used. In this paper we show that the row-column approach can be excessive in the number of multiplications and rotations. Moreover, we propose the novel approach based on natively two-dimensional base operators which allows for significant reduction in the number of elementary operations, i.e., more than twofold reduction in the number of multiplications and fourfold reduction of rotations. The additional computational costs that arise instead include an increase in the number of additions, and introduction of bit-shift operations. It should be noted, that such operations are significantly less demanding in hardware realizations than multiplications and rotations. The performed experimental analysis proves the practical effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

Discrete two-dimensional orthogonal wavelet transforms find applications in many areas of analysis and processing of digital images. In a typical scenario the separability of two-dimensional wavelet transforms is assumed and all calculations follow the row-column approach using one-dimensional transforms. For the calculation of one-dimensional transforms the lattice structures, which can be characterized by high computational efficiency and non-redundant parametrization, are often used. In this paper we show that the row-column approach can be excessive in the number of multiplications and rotations. Moreover, we propose the novel approach based on natively two-dimensional base operators which allows for significant reduction in the number of elementary operations, i.e., more than twofold reduction in the number of multiplications and fourfold reduction of rotations. The additional computational costs that arise instead include an increase in the number of additions, and introduction of bit-shift operations. It should be noted, that such operations are significantly less demanding in hardware realizations than multiplications and rotations. The performed experimental analysis proves the practical effectiveness of the proposed approach.

The paper investigates the result of v-scoring impact by laser radiation in water medium applied on silicon very large-scale integration circuits employed in hybrid photodetectors of infrared radiation. The width of material damage around the score line is established to be approximately 47 m. The appearance of hydraulic shock in the course of water boiling during v-scoring is discovered; its pressure on material is not less than kg/ m . [ABSTRACT FROM AUTHOR]

Triangular carbon nanotube (T-CNT) bundles are proposed as long interconnects for subthreshold VLSI circuits. The performance of subthreshold interconnects depends on the intrinsic quantum and electrostatic coupling capacitances of the interconnects. Proposed T-CNT bundles have the most optimum geometry that give least possible coupling capacitance between adjacent wires in an IC. First, we describe the T-CNT bundle models and of traditionally used square/rectangular CNT bundles for comparison. The subthreshold output current of an inverter is modelled, and hence, we find the optimum transistor widths for nFET and pFET that drives the subthreshold interconnects. This is carried out by the current-over-capacitance ratio approach, where the subthreshold current and the transistor output capacitance are considered. Then, we model the interconnects using equivalent single conductor models and find their propagation delay and power dissipated. The performance factors such as crosstalk-induced delay, power delay product and victim noise levels of capacitive coupled interconnects of T-CNT bundles are compared to traditionally used square/rectangular CNT bundles for lengths ranging from 500 μm to 2000 μm. We find that T-CNT bundles outperform square/rectangular CNT bundles. [ABSTRACT FROM AUTHOR]

In this paper, a method to reduce the effect on image quality caused by the parasitic resistance of column bus in high-resolution cMOS image sensors is presented. Through the mathematical model of the column bus, the effect on image quality caused by the resistance is analyzed. The resistance would cause two nonideal factors: dynamic swing reduction and nonlinearity. To reduce the effect of the nonideal factors, this paper utilizes a layout design by putting the readout circuit and column bias circuit on different sides of the pixel array. The relationship among the resistance, light intensity of input, and standard deviation of output gray levels is analyzed. In a 0.13- $\mu \text{m}$ CMOS process and a 12 cm $\times$ 12 cm pixel array, the simulation result shows that the resistance would cause column stripes or gradient under a traditional method. Under the proposed method, the peak standard deviation under uniform illumination decreases from 16.25 to 1.44. The peak signal-to-noise ratio increases from 64.66 to 91.64 dB and the structural similarity index increases from 0.79 to 0.97. The proposed method can enhance image quality for high-resolution image sensors significantly. [ABSTRACT FROM AUTHOR]

A new dynamical neuron model for low power and compact VLSI implementation is presented. The model is capable of generating the most common type of spiking patterns. Judicious use of subthreshold CMOS design techniques leads to a very effective low-power CMOS Neuron and synapse circuits. The circuit consists of a single first-order log domain filter and a few hyperbolic function generators. We have also developed a circuit which realizes the synaptic interconnections of the neurons. Based on this complete neuron and synapse model, we studied synchronization behavior of two reciprocally interconnected neurons with excitatory and inhibitory couplings. Owing to the use of log-domain design and current-mode design, the circuits occupying low chip area and having very low power consumption are obtained even at real biological time-scale operation. These features make these circuits especially suitable for hybrid interface applications and large scale VLSI neuromorphic networks. [ABSTRACT FROM AUTHOR]

Tunnel FETs (TFETs) having better ON–OFF switching performance is an alternative nano-device that replaces MOSFET (metal oxide field effect transistor) in low-power VLSI (very large scale integration) circuits. The physics-based models of TFETs are essential to integrate with circuit simulators for design and optimization of TFET-based circuits. There is no built-in TFET model available in any commercial circuit simulators. This paper presents the development of an accurate physics-based model for double-gate TFET and its integration in Cadence circuit simulator SPECTRE. The model captures all device physics and is evaluated for various device parameters such as channel length, oxide thickness, and high-κ dielectrics and validated with results from TCAD (Technology Computer Aided Design) Sentaurus. The integrated model is used to develop digital libraries of logic gates and adders. These digital libraries can be used to design TFET-based VLSI circuits. This method of integration using physics-based model of TFET, compared to look-up table approach which is purely data-driven, gives flexibility to circuit designers to design TFET-based low-power circuits taking into account the dependence on bias, temperature, scaling, and other process parameters. [ABSTRACT FROM PUBLISHER]

This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits, which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

Abstract: Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared. [Copyright &y& Elsevier]

Abstract: The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500MHz, highly non-uniformly distributed over the 2cm2 chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip. [Copyright &y& Elsevier]

Machine Learning techniques (ML) are being widely adopted in embedded devices due to their efficiency and flexibility. However, the strict power limitations in such devices, combined with the variable resource requirements of ML models, require further understanding of how model complexity affects power and performance. This paper proposes a framework that facilitates the design space exploration of dedicated decision trees (DT) and random forests (RF) accelerators by enabling a joint assessment of power dissipation and prediction accuracy. The proposed framework translates tree-based structures to hardware description languages (HDL). The HDL modules are submitted to logic and physically-aware hardware synthesis flows, allowing a detailed power-performance analysis of VLSI DTs and RFs. Using four data sets of embedded applications as case studies, we found that quantizing the input features leads to accuracy gains of up to 6.3% compared with the precise versions. We also show that using shallower trees may lead to small prediction loss with significant reductions in power, which is favorable for power-constrained applications. Our translator achieves better results in terms of energy/inference w.r.t. prior related works under comparison, one of which employed standard methods for hardware translation such as High-Level Synthesis. The proposed solution presents a power reduction of 10 times or more for the same inference throughput reported in prior works. [ABSTRACT FROM AUTHOR]

VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations. [ABSTRACT FROM AUTHOR]

Peak power reduction has been a critical challenge in the design of integrated circuits impacting the chip's performance and reliability. The reduction of peak power also reduces the power density of integrated circuits. Due to large IR-voltage drops in circuits, transistor switching slows down giving rise to timing violations and logic failures. In this paper, we present a new clock control strategy for peak-power reduction in VLSI circuits. In the proposed method, the simultaneous switching of combinational paths is minimized by taking advantage of the delay slacks among the paths and clustering the paths with similar slack values. Once the paths are identified based on the path delays and their slack values, the clustering algorithm determines the ideal number of clusters for the given circuit and for each cluster the maximum possible phase shift that can be applied to the clock. The paths are assigned to clusters in a load balanced manner based on the slack values and each cluster will have a phase shift possible on its clock depending on the slack. Thus, the proposed register-transfer level (RTL) method takes advantage of the logic-path timing slack to re-schedule circuit activities at optimal intervals within the unaltered clock period. When switching activities are redistributed more evenly across the clock period, the IC supply-current consumption is also spread across a wider range of time within the clock period. This has the beneficial effect of reducing peak-current draw in addition to reducing RMS power draw without having to change the operating frequency and without utilizing additional power supply voltages as in dual or multi VT approaches. The proposed method is implemented and tested through simulations using an experimental setup with Synopsys Tools Suite and Cadence Tools on the ISCAS'85 benchmark circuits, OpenCore circuits and LEON processor multiplier circuit. Experimental results indicate that peak power can be reduced significantly to at least 72% depending on the number of clusters and the phase-shifted clock identified as suitable for the given circuit by the proposed algorithms. Although the proposed method incurs some power overhead compared to the traditional clocking method, the overhead can be made negligible compared to the peak-power reduction as seen in the experimental results presented. [ABSTRACT FROM PUBLISHER]

Abstract: We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype. [Copyright &y& Elsevier]

Abstract: The transmission of data from detectors in future high energy experiments will be driven by a number of requirements. In many cases, raw bandwidth is the strongest of these but other needs such as diverse functionality, compactness, low power and radiation resistance are equally important. The GigaBit-Transceiver project has been launched to provide a solution to these problems. The aim is to deliver a chip-set to build a bidirectional optical link transmitting and receiving serial data at 4.8 Gigabit/s. The project is based on three integrated circuits; a trans-impedance amplifier to receive signals from a photo-diode, a laser driver, and a transceiver containing a high-speed serialiser and de-serialiser. All of these have been successfully prototyped, and this paper will focus on the design and results from the serialiser/deserialiser prototype. This has been designed in commercial 130nm CMOS with particular emphasis on enhancing its immunity to single-event-effects. The specific design features to achieve this will be described. The chip has been fully characterized in the lab, and jitter and bit-error-rate measurements are presented. The custom packaging of the chip will also be described together with the next steps foreseen in the project. [Copyright &y& Elsevier]

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology. [ABSTRACT FROM AUTHOR]

Abstract: The problem of computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is studied in this work. The proposed method is an approximate extended version of the method of images. The initial problem is formulated here as an optimization problem for the solution of which a genetic algorithm (GA) is employed. The proposed method is fast, general, does not rely on fitting techniques and is applicable to an arbitrary 2D or 3D geometry configuration of conductors. Extensive simulation results are presented for several practical case studies. Comparative results are given with other methods from literature and a commercial tool employing the Finite Element Method (FEM). The results show that the capacitance value computed by our method is in close agreement to the value obtained by the other methods from literature and also by the commercial tool with the average difference ranging between 2% and 5% while demonstrating better scalability as the problem complexity rises. [Copyright &y& Elsevier]

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. The method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveform. Noise peak and width expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is 4.1% and for the width is 6.8% while allowing for very fast analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~12% faster and requires ~69% less transistors. [ABSTRACT FROM AUTHOR]