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The effect of plastic mulch on chickpea (Cicer arietinum L.) cultivation under low head drip irrigation systems was studied at ICAR-Central Institute of Agricultural Engineering, PFDC, Bhopal during 2018-19. Drip irrigation system was operated by placing water tank at a total water deliver height of 3 m and varied heads to 2.5 m and 2.0 m to find out the value of coefficient of uniformity under these heads. The experimental treatments consisted in five levels by varying irrigation methods: Flood irrigation, irrigation with drip laid on raised beds, irrigation with drip laid on raised beds covered with black mulch, irrigation with drip laid on raised beds covered with silver mulch and irrigation with drip laid on raised beds covered with white mulch. Growth and yield parameters of chickpea viz., plant height (cm), number of branches per plant, plant dry matter (g/plant), effective nodule per plant and nodules dry weight (mg/plant), number of pods per plant, 100 seed weight, seed yield (kg/ha) and harvest index were highest under silver plastic mulch laid on raised beds, irrigated with drip as compared to black plastic mulch and white plastic mulch treatments. Lowest growth and yield parameters were recorded in the flood irrigated treatment. Water Use Efficiency was highest under silver plastic mulch (17.21kg/ha mm) and lowest under flood irrigated condition (3.74 kg/ha mm). Net returns were higher in the treatment under the silver mulch (Rs/ha 77939) and followed by black mulch (Rs/ha 67179) with lowest net returns in the flood irrigated condition (Rs/ha 32690).

This paper presents a demonstration of the superiority in overall sensitivity of a V-shaped attachment structure used in the design of a 3-axis piezoresistive micromachined accelerometer. This is accomplished through a detailed comparison of generated maximum stress values in different similar designs reported in the literature. All these structures are composed of a seismic mass attached to the substrate with four arms. The structure uses four V-shaped arms with a short fragment located in their middle. The analysis on the V-shaped structure shows that maximum values of induced stress under acceleration in the axes are higher than those given by other structures used in the comparison study. This stress values enhancement is more pronounced for accelerations on the z-axis. Simulated structures used in the comparison study give maximum z-axis stress values of 0.5 MPa and 0.09 MPa while the V-shaped structure's value is 4.25 MPa. In addition, the Ax and Ay accelerations induce in our structure two different paths for maximum stress offering added sensitivity.

In this work, the fracture of spin coated SU-8 epoxy thin films was investigated under mode I loading using in situ optical experiments on specimens with double edge notched tensile geometry. A method was developed to fabricate 3 μm thick SU-8 films with tapered Chevron type notches using a combination of electron beam and ultra-violet lithography techniques. Subsequently, through speckle patterning under tensile loading, the local deformation fields around the crack tip were extracted using digital image correlation. Since the notches were tapered through the thickness, a crack nucleated from them and grew stably until it spanned the entire thickness before propagating unstably leading to catastrophic failure. As SU-8 underwent brittle fracture with no evidence of a large process zone, the critical energy release rate, J I C was computed from deformation fields, and was found to be 106.6 ± 12.03 J /m 2. As the film thickness was small compared to lateral dimensions, assuming plane stress conditions, the critical stress intensity factor was calculated as 0.57 ± 0.03 MPa $\sqrt {m}$ . Furthermore, to assess the validity of the experimental method, a finite element simulation on the exact specimen geometry was conducted with experimentally evaluated far field displacement boundary conditions. The strain fields and J-integral value obtained from the simulation were in good agreement with the experimental results, implying the validity of the in situ experimental method proposed given the challenges of small scale specimens. Furthermore, using fractography and optical imaging it was confirmed that the unstable crack propagation started once the crack front reached full thickness, thereby providing sharp crack at the time of failure, which is necessary for brittle materials for valid fracture toughness experiment. It is expected that the proposed methods of specimen preparation and fracture experiments on microscale polymer thin films can be used on other materials.

This paper examines how the use of genebank materials has changed from 1996 to 2006 using a similar survey by Dudnik et al. (2001) of reports published in 1996 as a baseline. Articles published in four journals generally used by genetic resource scientists were analyzed in each 2006 issue, as was done by Dudnik et al. in 2001. Studies involving genebank materials were selected and the following data were recorded: species used, locations of studies, affiliation of researchers, sources of the materials and their uses. The analysis identified 320 studies in which a total of 57,935 accessions from 148 genebanks were used. Crop wild relatives were targeted in 20% of the studies. The study showed that a much higher percentage of accessions came from developed (87%) than from developing countries (7 %), while 6% were supplied by CGIAR centers. The results in 2006 revealed an increase in the proportion of studies using genebank materials as compared to 1996. Genebank materials were used primarily for studies of genetic diversity, agro-morphological and nutritional quality characteristics, biotic resistance, and mapping. Of the institutions carrying out the studies, 93% were from the public sector. However, there are still some barriers that limit the exchange of germplasm across borders. This implies that greater awareness among policymakers will be needed tofacilitate the necessary exchange of plant genetic resources between countries to improve agricultural production.

Atherosclerosis (stenosis) is a common cardiovascular disease in which the blood vessel restructures by narrowing, thickening and gets hardened due to the deposition of plaque. A detailed study of narrowing of arteries applying computational aspects which leads to better findings in order to know the underlying mechanics of development and progression of such diseases. Such kind of analysis can be a useful tool for the medical professionals to study the realistic physiological conditions. They can simulate and observe the blood flow in arteries. In the present study, a case of normal and stenosed carotid bifurcation is simulated. The models are generated in CATIA based on the clinical data obtained from a patient using Ultrasound Doppler. A transient FSI analysis considering Newtonian behavior is performed to compare the significance of High Blood Pressure (HBP) and Normal Blood Pressure (NBP) on carotid bifurcation. The FSI simulation is carried out for both HBP and NBP conditions for several pulse cycles on normal and stenosed models using ANSYS13.0 to demonstrate the changes in flow behavior at various sections of the model. The computed results agree well with clinical observations and available literature as seen in case of NBP.

Global climate change is anticipated to have a tremendous influence on crop productivity and nutrient cycling in legume-based cropping systems. The effect of long-term application of manure and fertilizers on the dynamics of soil organic carbon (SOC) pools and soil physical properties was studied in a soybean (Glycine max Merr. L)–wheat (Triticum aestivum L.) system. The temperature sensitivity of C pools and the alterations in microbial composition were determined at 25, 35, and 45 °C. Higher levels of microbial biomass C (MBC) and nitrogen (MBN), water soluble carbon (WSC), acid hydrolysable carbohydrates (AHC), particulate organic matter carbon (POMC) and nitrogen (POMN) were observed in the NPK + FYM at a depth of 0–15 cm. Irrespective of the treatment, micro aggregates (53–250 μm) were a major aggregate size class, comprising 45–57% of the total soil aggregates, followed by macro aggregates (250–2000 μm at 37.8–45%). Microbial respiration rate increased by 13.9% in most recalcitrant pools (

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.

KEYWORDSFamily studies; twin studies; adoptee; candidate genes; case-control studies; linkage studies; SNPs; GABA; Dopamine system; CYP2E1; Alcohol dehydrogenase ABSTRACT Alcoholism is an extremely complex disease for which no generally accepted definition exists. There is a complex interaction between the socio-environmental context, the individual at risk, and the availability of alcohol. The result of family, twin and adoption studies suggest a significant genetic predisposition to the disease. Identifying novel genetic risk factors for common diseases is a global challenge in the post genomic era. Recent molecular genetic research into the causes of alcoholism has drawn attention to the potential role of alcohol and acetaldehyde metabolizing enzymes. Functional polymorphisms have been observed at various genes encoding these enzyme proteins that act as one of the biological determinants significantly influencing drinking behavior and the development of alcoholism and alcohol-induced organ damage. Most ethanol elimination occurs by alcohol dehydrogenase (ADH) and aldehyde dehydrogenase (ALDH) systems via oxidation of ethanol to acetaldehyde and acetic acid. However, the legacy of alcoholism among certain ethnic groups suggests that genetic factors can increase an individual's vulnerability for this disease. An association study in patient cohorts and controls, from large populations involving whole genome scans, is the preferred approach for complex traits. To understand the molecular epidemiology and role of cofactors in alcoholism the standard phenotype-genotype correlation may be a useful tool. The present paper reviews various aspects of alcoholism including both the behavioural and molecular etiologies.

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors., IEEE

Japan was one of the world's early adopters of broadband Internet access technologies, notably ADSL. Although last year it lost its number one global ranking to China, ADSL deployment in Japan continued to grow. This growth has been tied to ever increasing ADSL bandwidths. Centillium Communications has been in the unique position for many years of a major contributor to this rapid growth, pioneering many new technologies in ADSL, with a ringside seat to observe how competition has stimulated some of these technology advances. This article reviews some of the technologies behind the rapid market growth and provides an overview of directions in which these technologies are shaping the future of ADSL in Japan.

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better Vth-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (gmRo) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs., IEEE

Morphological and genetic variation of manau rattan (Calamus manan, Miq.) studies have been conducted in three provinces in Sumatra, Indonesia, i.e. in Bengkulu, in Jambi, and in West Sumatra Province. Distinctive variations such as the presence of vestigial flagellum and red colour of rachis, as opposed to no vestigial flagellum and the normal green colour of petiole and rachis, were noted in certain individuals in wild manau rattan populations, although the percentage was only 5-60%, depending on the sites. These variations, which were confirmed with isozyme analysis results, are based on 6 enzyme systems, i.e. PGD, PGI, MDH, IDH, PER and EST out of 10 systems analysed. The range of percentage of polymorphic loci was 66.67-76.67%. The highest genetic diversity (He = 0.34) was West Sumatra Province which was mainly contributed by the Siberut Island, followed by Jambi Province (He = 0.28). Based on a dendogram constructed, the relatedness and genetic distance between studied populations in Sumatra could also be determined.

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs., IEEE

CASE A 75-year-old man underwent intramedullary nailing for an unstable intertrochanteric fracture of the left hip. After surgery and postoperative recovery, he was transferred to a rehabilitation ward. He was able to mobilize at 2 days postoperatively; at 2 weeks postoperatively, he developed the sudden onset of tachycardia, hypotension, and a large hematoma on the left thigh. Following immediate resuscitation, a computed tomography (CT) angiogram demonstrated a bleed from a branch of the profunda femoris artery. The 3-dimensional CT reconstruction implicated the displaced lesser trochanter osseous fragment as the cause of the hemorrhage. CONCLUSION Surgeons should be aware of this rare complication and the possible etiology of fracture displacement as the cause of a delayed-onset bleed after intramedullary nailing, and they should also be cognizant of the subsequent optimal management.

In the title compound, C24H14Cl2N2O2S, the 2H-chromene ring system is approximately planar, with a maximum deviation of 0.025 (2) Å. The thiazole ring is almost planar, with an r.m.s. deviation of 0.0022 Å, and makes a dihedral angle of 58.52 (7)° with the chromene ring system. The chromene ring system is inclined at angles of 58.3 (1) and 55.39 (9)° with respect to the two chlorophenyl rings. The two chlorophenyl rings show significant deviation from coplanarity, with a dihedral angle between them of 47.69 (8)°. The crystal structure features C—H...Cl interactions extending in (100) and propagating along thea-axis direction and weak π–π interactions [centroid–centroid separation = 3.867 (2) Å].

Conformational properties of 2',5'-linked 3'-deoxyribonucleotides have been compared with their natural isomer using CD spectroscopy. It is inferred from the salt induced titration curves that the 2',5'-linked-3'deoxyribonucleotides have rigid phosphodiester backbone.

In the title compound, C14H11N5OS2, the triazolo–thiadiazole system is essentially planar (r.m.s. deviation = 0.002 Å) and makes dihedral angles of 6.33 (12) and 42.95 (14)° with the planes of the oxazole and phenyl rings, respectively. In the crystal, face-to-face π–π interactions are observed between the thiadiazole and oxazole rings [centroid–centroid distance = 3.4707 (18) Å], leading to columns along [010].

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's., © IEEE

In this letter, the low-frequency noise performance of single-halo (SH) devices is reported, and the physical mechanisms are identified. Experimental results show that, at constant gate overdrive voltages, SH devices show reduced low-frequency noise levels compared to the conventional devices. However, under constant current bias conditions, the noise reduction is less substantial. Low-frequency noise dependence on channel length is also investigated for SH devices based on the electrical measurements and analytical calculations.

It has been recently recognized that the nonisothermal conditions present in physical vapor transport ampoules can give rise to a slip flow of gas over the side walls of the ampoule. This phenomenon, known as thermal creep, is usually insignificant relative to buoyancy-induced flows under similar nonisothermal conditions, and has therefore been neglected in previous PVT numerical models. However, thermal creep can, in principle, become a dominant convection mechanism in buoyancy-free environments such as those encountered in microgravity experiments. We present here a numerical investigation of the effects of thermal creep on the growth process in axisymmetric, binary component PVT systems. A continuum-based model, which includes buoyancy and Soret diffusion, is developed. We show that thermal creep can result in recirculating bulk flows within the ampoule. For relatively high values of the Schmidt number and large wall temperature gradients, these flows can result in significantly nonuniform distributions of mass flux at the crystal interface, and can also be comparable to or exceed the flow velocities generated by buoyancy under normal gravity. The effects of thermal creep on buoyant convection, and on the Soret transport of the vapor, are examined.

Using detailed experimental data, we demonstrate that for the correct interpretation of negative bias temperature instability (NBTI) degradation behavior with stress time, it is essential to include the effect of trapping of hydrogen species in the oxide. A new oxide trap-assisted NBTI degradation model is proposed and shown to fit the experimental data very well. Our proposed model can also be used to explain the recently observed phenomenon of higher NBTI degradation for increasing nitrogen concentration in the oxide. We show from numerical calculations that, for higher nitrogen concentration at the interface, one would expect higher NBTI degradation, as also reported recently.

In this letter, we analyze the suitability of the double gate MOSFETs (DG MOSFETs) for RF-mixer applications from the point of optimizing the transconductance gain, power consumption, and area. Mixer topologies using the 0.13-μm conventional MOSFETs, simultaneously driven DG MOSFETs (SDDG) and the independently driven DG MOSFETs (IDDG) are compared using extensive device simulations. In the frequency range 1-40 GHz, our simulation results show that the mixer circuits realized using the SDDG technologies show an order of magnitude lower power-area product, for a given transconductance gain, compared to the conventional and the IDDG technologies., IEEE

The EPA-recommended toxicity equivalence factor (TEF) approach to estimating the lifetime incremental cancer risks for dioxins does not address (a) differences in the severity of toxicity according to the composition of chemical mixture and (b) potentials for modification of tissue-level doses of congeners in mixtures and consequently the cancer risk estimates. Our earlier efforts to model the binding of congeners to the Ah receptor in the low-dose range and to develop quantitative estimates for the formation of fractions of Ah receptor-congener complexes resulted in the definition of a unique parameter, defined as competitive binding ratio (CBR), to adjust tissue-level doses for mixture exposure. We made an effort to incorporate CBR values in the dose-response analysis and risk characterization of congeners in two distinct exposure scenarios. The modified approach to estimating tissue-level doses of congeners in mixtures by the use of a competitive binding model indicated that (a) the Ah receptor affinity is an important criterion in the determination of tissue-level dose of congeners, (b) the TEF doses calculated by using the model algorithms modified the tissue-level doses for congeners in mixture exposures, and (c) the combined lifetime incremental cancer risks for all congeners were generally lower when model algorithms were used in the dose-response analysis. However, the percentage contribution of toxic congeners was significantly higher when model algorithms were used. The percentage contribution of higher congeners with low toxicity was considerably reduced when model algorithms were used.(ABSTRACT TRUNCATED AT 250 WORDS)

With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit performance. To miti-gate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, Fin FET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device, since, such Fin FET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the performance enhancement with such Fin FET Device for Mux Circuit, and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.

Using high-k material in a gate dielectric stack, low-operating-voltage organic semiconducting material sensors for determining total dose radiation are proposed. To improve the stability of organic semiconducting layer in the atmospheric conditions, a thin silicon nitride layer deposited by hot-wire CVD process was used as a passivation layer. Furthermore, in order to achieve higher sensitivity, a parallel connection of organic field-effect transistors (OFETs) is explored in this letter. These sensors are exposed to ionizing radiation using a cobalt-60 radiation source for different total dose values. A three-times improvement in sensitivity was observed in the off current with a three-OFET array.

In this letter, the integration of a high-k gate dielectric has been demonstrated for achieving low-operating-voltage organic field-effect transistors (OFETs) and circuits based on solution-processed poly(3-hexylthiophene) (P3HT). We have successfully demonstrated all-p-type organic circuits based on P3HT operating at below 4 V supply voltage. The switching behavior is improved by using the bootstrapping technique, with the boot-strapped inverter showing good results with a dc gain (A(v)) of -1.7 and V(OH) and V(OL) values of 3.3 and 0.35 V, respectively. The output swing of the bootstrapped inverter is improved by about 40% when compared to that of simple all-p-type inverters, as demonstrated by using experimental characterizations.

The electron velocity overshoot phenomenon in the inversion layer is experimentally investigated using a novel thin-film silicon-on-insulator (SOI) test structure with channel lengths down to 0.08 /spl mu/m. The uniformity of the carrier density and tangential field is realized by employing a lateral asymmetric channel (LAC) profile. The electron drift velocity observed in this work is 9.5/spl times/10/sup 6/ cm/s for a device with L/sub eff/=0.08 /spl mu/m at 300 K. The upward trend in electron velocity can be clearly noticed for decreasing channel lengths.

Pentacene organic field effect transistors are fabricated using polymethyl methacrylate (PMMA) as a gate dielectric on flexible polymeric substrates like the indium tin oxide coated polyethylene terephthalate (ITO coated PET), and polyethylene napthalate (PEN) in top contact configuration. The ITO and aluminium (evaporated on PEN) act as the gate materials for the OFETs. The devices on ITO coated PET show electron mobility up to 0.07 cm2/V-s and the on/off ratios in the order of 103.

In this paper, with the help of simulations the concepts of source/drain (S/D) impurity profile engineering are proposed for reduction of the junction capacitance (Cj). It has been recently shown that it is possible to realize the benefits of PD- SOI technologies with the help of Source/Drain On Depletion Layer (SDODEL) MOSFETs, employing the bulk technologies. Here, for the first time, we investigated analog performance improvement with Single Halo SDODEL MOSFETs, as well as Double Halo SDODEL MOSFET and compared their performances with Double Halo MOSFETs (which will henceforth be referred as Control MOSFETs) with extensive process and device simulations. Our results show that, in Single Halo SDODEL MOSFET there is a significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I D etc.) for sub 100nm technologies.

Interface state generation and threshold voltage degradation for various channel length devices, stressed at different drain bias conditions, has been studied. It is found that the NBTI (negative bias temperature instability) effect decreases at low drain bias due to decrease in effective gate bias near the drain edge. The subsequent increase in degradation at higher drain stress bias is due to non-uniform generation of interface states and subsequent diffusion of generated hydrogen species along the length of the channel. This effect is more pronounced for short channel devices stressed at high temperatures and high drain bias.

Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-/spl mu/m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device., IEEE

Forward body bias has been shown to be an effective way to improve the digital performance of CMOS circuits. However, as the technologies scale into the sub 100 nm regime, body bias sensitivity degrades, making the application of body bias less attractive for scaled CMOS technologies. In this work, we show for the first time that, Single Halo (SH) MOSFETS exhibit superior body bias sensitivity in the sub 100 nm regime compared to conventional technologies, which can be utilized for improving the performance of forward body-biased MOS devices such as dynamic threshold (DTMOS) and body-driven (BDMOS) transistors for low-voltage (LV) analog designs with the scaled technologies. Our result show that SH doping in these devices results in more than 50 % improvement of intrinsic gain and about a factor of two improvement in transconductance for DTMOS and BDMOS devices respectively, compared to their conventional counterparts.

This paper discusses the effect of localized charge storage on sub-threshold swing and threshold voltage in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cells. By analyzing the change in potential contours, it has been shown that the change in sub-threshold swing is correlated to fringing of electric field lines, and hence to the gate-to-substrate capacitance.

The role of initial interface damage for negative bias temperature instability (NBTI) degradation has been examined for short channel MOSFET devices. In this paper we present a detailed study of the role of initial silicon-oxide interface quality on the NBTI degradation. Hole density and oxide fields are important parameters responsible for NBTI degradation. Our results show that NBTI degradation is independent of initial interface quality.

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluation of circuits directly from device simulation results without going through model parameter extraction.

The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS scaling into the sub-100 nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately for low power operation. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to the problems involved in Sub-100 nm device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel implementation of Electrically Induced Junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed DC as well as transient simulation results bring out the advantages of this novel structure.

This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.

The effect of channel hot carrier (CHC) stress under typical analog operating conditions is studied for the first time for single halo (SH) p-MOSFET devices. The SH devices show less degradation under identical operating conditions compared to conventional MOSFETs. The effect of SH implant parameters on device degradation is presented.

In this paper, a new method for measuring border trap density (nBT) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which nBT is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap., IEEE

SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices. To reduce the source/drain parasitic resistance, a novel salicide technology with Ge pre-amorphization is used (Hsiao et al, IEEE SOI Conf., p. 126, 1996).

Design For Diagnostics (DFD) is critical for rapid silicon debug of new product and ramping to high volume manufacturing. I feel two aspects of DFD are important. The first enables software fault localization tools that quickly localize to the failing node (this includes ad hoc DFT methods, scan etc.). The second type of DFD enables success with physical localization tools. This includes designed in physical features to enable rapid bug verification with focused ion beam milling, and probe points for internal signal probing. Both types of DFD are needed and complement each other in the different phases of silicon debug and root cause analysis.