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NMOS transistor structures are widely used in IC's. Many manufacturing processes and operations are used in the production process. It is important to choose and deliver technological process (TP) parameters necessary for production for IC design. In this case, the problem addressed is redistribution of structures after a number of TP. So, the optimization of technological manufacturing processes of NMOS structures, and hence the channel area, is important. High-temperature TP (oxidation, diffusion, etc.) have been examined in previous works [4,9]. This paper will focus in the optimization of the channel formation by way of ion implantation (II). A variety of simulations are used for the optimization in the design phase. In this paper, the simulation is performed using ATHENA software package. It is also important to choose and propose the algorithms for optimization of technological processes. This paper offers an optimization algorithm for choosing the modes of II.

MOS transistor structures are widely used in modern integrated circuits (IC). Different manufacturing methods are used. Many problems, such as the length, width of the channel, the overlap of source and drain areas with gate area, the diffusion of impurities after HTTO (high temperature technological operations). The solutions for all these problems are based on the mode of manufacturing processes and its optimization, and that is another problem. In this paper, models are selected and described and the results of modeling are presented. These models evaluate the influence of lateral implantation modes for MOS transistor output characteristics, and the influence for MOS transistor output characteristics. Technological structure problems which appeared in modeling of the exact case MOS are analyzed.