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The paper is dedicated to influence of the rapid thermal treatment of the gate dielectric at a temperature of ~1100 °С on the electrical parameters of the programmable time device with a correction of 512PS8. As the analyzed parameters of the given integrated circuit, the authors have selected breakdown voltage, gate leakage current, charge value of the gate dielectric breakdown with its thermal field tests performed. The breakdown voltage of the p-channel of the test transistor was measured by applying the linear voltage sweep from 0 to -100 V with the step of -0,5 V with the grounded drain and source. The leakage current of the gate Ig leak was determined at the gate voltage of -20 V. For evaluation of the charge properties of the gate dielectric of devices the, the thermal field tests were performed. The quality and reliability of the gate dielectric the authors the breakdown charge control was carried out (Qbd). It is shown that the rapid thermal treatment of the gate dielectric at a temperature of ~1100 °С during 7 s with its presence on the non-working side ensures the breakdown charge value of 2,040 C/cm2, and with its absence - 2,230 C/cm2, while during the standard process of creating the given integrated circuit this value constitutes 1,230 C/cm2. This means that the most efficient influence on the improvement of quality and reliability of the gate dielectric is ensured by its rapid thermal treatment when missing the silicon dioxide on the non-working side of the wafer. As compared with the standard process of their fabrication, carrying out such treatment allows 5,29 times reduction of the gate leakage current, 3,50 times reduction of the charge states and 1,07 times enhancement of the reliability of the p-channel transistor, and for the n-channel transistor the given values constitute 10,67, 3,50 and 1,81 times, respectively. It is established that the reliability improvement for the CMOS integrated circuits of time devices during the rapid thermal treatment of the gate dielectric is determined by a step-up of its breakdown charge owing to the more perfect microstructure of dielectric, resulting in the rebuild of the charge states both in the bulk and on the boundary with silicon.

The paper is dedicated to investigation of the influence of rapid thermal treatment on the microstructure of platinum silicide. The Pt films 43.7 nm thick were applied on the substrates of the monocrystal silicon by means of the magnetronic sputtering of platinum with the purity of 99.95 % on the МРС 603 set-up with the cryogenic pumping to the pressure not worse than 5*10-5 Pa. As an operating medium, argon was used with the purity of 99.933 %. Rapid thermal treatment of samples was performed in the thermal balance conditions by irradiating the non-working side of the wafer with the incoherent light flow in the nitrogen atmosphere during 7 s at the temperatures of 200-550 °C. The irradiation source in the set-up was represented by the quartz halogen incandescent lamps. The comparative analysis was done through the traditional long thermal treatment of the platinum films at a temperature of 550оС for 30 min in the nitrogen atmosphere. Investigations of the platinum silicide microstructure were performed by means of the transmission electron microscopy which demonstrated that the increase in the RTT temperature initiates first the annealing of defects on the inter-grain boundaries, which is evident from the more distinct contrast from the grains, and then one can observe their growth reflecting the forming of the new phase (silicide one). Such progress of changes of the platinum silicide microstructure and of the size of the grains with the increase in treatment temperature is determined by the heat of its forming. As the Pt2Si phase forming heat is minimum and constitutes 10.4-16.8 Kkal/atom of metal, and for PtSi - 15.7-25.5 Kkal/atom of metal, then the forming of a stable PtSi structure requires a higher temperature. The authors carried out calculations of the activation energy of the diffusion synthesis of platinum silicide during rapid thermal treatment. The calculations show that it is 0.37 eV smaller, than during the long thermal treatment. This means that in this case this process is subject to acceleration related to the rupture of the silicon-silicon bonds and electron excitation in silicon under the influence of the photon flow.

The paper is purposed to establish the principles of the micro-structural changes of Pt-Si system during the rapid thermal treatment. The Pt films 43.7 nm thick were applied on the substrates of mono-crystal silicon KEF 0.5 with orientation (111) by means of the magnetron platinum target sputtering (purity of 99.95 %) on the unit MPC 603 with the cryogen pumping to the pressure of no less than 5∙10-5 Pa. Argon was used as a working medium, whose purity constituted 99.933 %. Rapid thermal treatment was performed in the mode of the thermal balance with irradiation of the reverse side of the wafer by means of the non-coherent light flow in the nitrogen medium within the temperature range from 200 to 550 °C with a step of 50 °С during 7 s. In parallel, the solid phase synthesis was performed of platinum silicide by means of the standard method with application of the continuous single stage thermal treatment in the analogue medium (T = 550 °C, t = 30 min). Temperature monitoring was performed by means of the thermal couple method with accuracy of ±0.5 °C. The grain size was determined by the translucent electron microscopy method. Thickness of platinum silicide under formation, its surface micro-relief and the separation boundaries with silicon were determined by means of the raster electron microscopy. It is demonstrated, that with the rise of the rapid thermal treatment one can observe growth of the platinum film on silicon. A comparative analysis was conducted of the average size of grains, micro-relief of the PtSi surface and its separation boundary with silicon for two methods of its formation with application of the rapid thermal treatment and with application of the traditional continuous thermal treatment at the temperature of 550 °C during 30 min in the nitrogen atmosphere. By means of the raster electron microscopy method it is demonstrated, that size of the micro-relief on the separation boundary of PtSi-Si does not exceed 15.9 nm and the size of grains is 37.7 nm. This is in 2.5 and 3.1 times smaller, then in the case of the traditional single stage continuous thermal treatment.

Приведены результаты исследований влияния быстрой термической обработки подзатворного диэлектрика на параметры мощных p - и n -канальных MOSFET транзисторов. Установлено, что данная обработка позволяет за счет улучшения зарядовых и структурных свойств диэлектрика уменьшить токи утечки затвора и повысить надежность приборов.

The results of studying of the impact of formation modes of platinum silicide using qiuck heat treatment on electrophysical parameters of Schottky diodes are presented. It is shown that this treatment, as compared to the traditional one, allows at the cost of reducing of microrelief of boundary of PtSi–Si, and also obtaining as a result of treatment a less defective and equilibrium structure of the barrier layer, to raise barrier height from 0,804 to 0,825 V, to reduce leakage current from –4,42·10-6 to –2,85·10-6 A and in 1,25 times and to raise the reliability of Schottky diodes at operating temperature 125 °C.

Assessment is performed of the permissible nonuniformity of irradiation and temperature scatter as per the wafer area during the rapid thermal treatment, not causing the thermal stresses in it, resultant in the plastic melting or silicon disruption. It was shown, that formation of platinum silicide at Т≤ 810 °С does not cause the negative phenomena in silicon, and it should be performed in the nitrogen environment, whose flooding into the the sealed chamber is done after creation in it of vacuum of 10 –2 mm, mercury column.

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.

The method was suggested and the laser control set-up was developed of the arrow bend and bend profile of the semiconductor wafers. It was established, that on the basis of determining the inclination angle of tangent at any point of the surface due to deflection registration of the r eflected laser beam from the position, corresponding to reflection from the ideally plat surface, by means of its scanning by one of the wafer diameters it is possible to determine its bend profile.