42 results on '"Upadhyaya, Parag"'
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2. A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications
3. A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies
4. A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
5. A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET
6. Amplifiers in RF Transceiver for Wireless Communication
7. A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET
8. Crosstalk Associated with the Mingling of Current Returned Paths through the Vertical Bonding Structures
9. A 112-GB/S PAM4 Transmitter in 16NM FinFET
10. A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET
11. A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
12. A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
13. A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
14. Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET
15. A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS
16. A 0.5–16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET
17. A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET
18. A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
19. 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET
20. A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET
21. Novel MOS varactor device optimization and modeling for high-speed transceiver design in FinFET technology
22. A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS
23. A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET
24. 3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET
25. A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS
26. 3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
27. Device aware high-speed transceiver design in planar and FinFet technologies
28. Wideband flexible-reach techniques for a 0.5–16.3Gb/s fully-adaptive transceiver in 20nm CMOS
29. 2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS
30. A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs
31. Design Techniques for Load-Independent Direct Bulk-Coupled Low Power QVCO
32. Design of high-speed wireline transceivers for backplane communications in 28nm CMOS
33. A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS
34. Enhancement technique of insertion loss and linearity for PIN diode switches
35. Silicon-based PIN SPST RF switches for improved linearity
36. Low phase noise load independent switched LC VCO
37. A 1.1V Low Phase Noise CMOS Quadrature LC VCO with 4-Way Center-tapped Inductor
38. A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module
39. A 1.3V Low Phase Noise 2-GHz CMOS Quadrature LC VCO
40. Low phase noise load independent switched LC VCO.
41. Load independent bulk-coupled low power quadrature LC VCO.
42. Silicon-based PIN SPST RF switches for improved linearity.
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