664 results on '"Un-Ku Moon"'
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2. An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting.
3. A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC.
4. PLL-SAR: A New High-Speed Analog to Digital Converter Architecture.
5. A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting.
6. Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC.
7. Passive Third Order Continuous-Time ΔΣ Modulator with Q Enhancement Technique.
8. Switched-Capacitor Circuits.
9. A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS.
10. A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting.
11. Low-Distortion Correlated Level Shifting Sample-and-Hold Stage.
12. Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR.
13. A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators.
14. Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR.
15. An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier.
16. Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model.
17. Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators.
18. Cascoded Ring Amplifiers for High Speed and High Accuracy Settling.
19. Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL.
20. A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique.
21. A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter.
22. A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
23. Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers.
24. Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit.
25. A Power Efficient SAR Algorithm for High Resolution ADCs.
26. An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs.
27. Power Optimized Comparator Selecting Method For Stochastic ADC.
28. A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier.
29. Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits.
30. A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.
31. A multi-path ring amplifier with dynamic biasing.
32. A highly compact wideband continuous-time transimpedance low-pass filter.
33. Voltage domain correction technique for timing skew errors in time interleaved ADCs.
34. Pseudo-pseudo-differential circuits.
35. A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.
36. A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.
37. A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling.
38. A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier.
39. An Oversampling Stochastic ADC Using VCO-Based Quantizers.
40. Data converter reflections: 19 papers from the last ten years that deserve a second look.
41. A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
42. A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.
43. A VCO-based spatial averaging stochastic ADC.
44. Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters.
45. Analysis of metastability errors in asynchronous SAR ADCs.
46. A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW.
47. A ΔΣ ADC using an LSB-first SAR quantizer.
48. Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers.
49. Selectable starting bit SAR ADC.
50. Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement.
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