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In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra-thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.

We experimentally demonstrate BEOL compatible ( $\mathrm{I}_{\mathrm{D},\mathrm{SAT}}$ of $370\mu\mathrm{A}/\mu\mathrm{m}$ , and on-off ratio> 4×109 at $\mathrm{V}_{\mathrm{DS}} =1\mathrm{V}$ and $\mathrm{V}_{\mathrm{GS}}-\mathrm{V}_{\mathrm{T}}=2\mathrm{V}$ We provide insight into the electrostatic gate control efficiency through temperature and frequency dependent admittance measurement. We identify fundamental transport mechanisms that limit electron mobility inamorphous IWO as a function of gate-bias $(\mathrm{V}_{\mathrm{GS}})$ and temperature. Benchmarking shows that IWO DGFET is a promising BEOL transistor for enabling high-performance monolithic three-dimensional (M3D) integrated circuits.

The ultra thin body (UTB) SiGe on insulator (SGOI) substrate with body thickness of only 5 nm has been fabricated by hetero-layer transfer technique with highly selective wet etching. According to Raman spectroscopy, UTB-SiGe layer with Ge fraction of 67% and +1% partially tensile strain was transferred onto the SiO2/Si host substrate without the strain degradation. To present the feasibility of UTB-SGOI substrate, a well-behaved performance of 2-μm-gate-length normally off UTB-SGOI nMOSFET has also been demonstrated.

An inspiring UTBB SOI MOSFET structure with enhanced immunity to the drain-induced barrier lowering (DIBL) is analyzed. The structure includes the dual-gates in the lateral direction. The voltage difference is applied between the dual-gates, through which the electrostatic potential and the energy band along the channel are modified and the electrical performance is boosted. The electrical characteristics are investigated by measuring the electron concentration, the conduction band energy level, and the potential at the front-surface. The impact of the negative voltage bias applied to the right gate on the performance of the new device is studied, and compared to that of the conventional ultra-thin body ultra-thin box silicon-on-insulator (UTBB SOI) devices. The results reveal that the undesirable DIBL values are lower in this innovative device than that in the conventional UTBB SOI MOSFET.

Total ionizing dose (TID) effects in ultra-thin body Ge on Insulator (GOI) junctionless CMOSFETs with recessed source/drain and channel have been studied. 10-keV X-ray irradiation leads to net hole trapping at the top and bottom Ge/dielectric interfaces of both GOI NFETs and PFETs. The Ge channel thickness and post-oxidation processing can strongly affect the radiation response. Application of negative back-gate bias can moderate the radiation-induced threshold-voltage shifts.

The carrier scattering mechanisms are quantitatively examined for UTB Ge-OI pMOSFETs. It is confirmed that the μ fluctuation is dominant for Ge-OI pMOSFETs thinner than ~5 nm and the μ ph /μ sr are dominant for thicker channels of >~8 nm.

A computational study at atomic level was performed for negative-capacitance MOSFETs (NC-FETs) with ultrathin body silicon (UTB-Si) and monolayer MoS 2 as channel materials and HfO 2 as ferroelectric layer material. $\sim 25$ mV/dec average subthreshold slope $( SS)$ for at least 4-order current was observed in MoS 2 NC-FET and shows steeper slope comparing to the Si cases, which is attributed to both tunneling current and negative capacitance effect. Based on our investigation, 1L-MoS 2 FEFETs could be the candidate for low-power application (LP) in next generation FETs.

This paper reports an ultrahigh-sensitive ISFET sensor that is developed using TCAD model of the industrial 22-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. The modeling method is exploited by changing the potential surface charge depending on the electrolyte pH change and investigating how will it cause the threshold voltage shift of ISFET device and other transfer characteristic parameters. The properties of a user-defined material offered by Silvaco are exploited to simulate the electrolyte behavior. The parameters of silicon semiconductor material (i.e., energy bandgap, permittivity, affinity, and density of states) are set to reconstruct an electrolyte solution. The electrostatic solution of the electrolyte area is investigated by giving a numerical solution for the semiconductor equation inside this area. On the other hand, the strong electrostatic coupling between the front gate and the back gate of FDSOI devices provide an intrinsic signal amplification feature for sensing applications. Utilizing a layer deposited Titanium dioxide (TiO2) as a pH sensing film, pH sensors having a sensitivity ∼1250 mV/pH is reported. The small sensing area and the FDSOI-based technology of the device make the sensors ideal for the IoT market.

The read and write stability of SRAM cell depends on the high-performance CMOS technologies (FD-SOI technology), due to low power dissipation, and high switching and inter-die variability. This paper first analyzed the electrical behavior of ultrathin body fully depleted silicon-on-insulator (UTB FD-SOI) MOSFET. It is demonstrated that the FD-SOI MOSFET has high Ion to Ioff ratio (better switching) and low threshold voltage. By taking into account of high switching of UTB FD-SOI MOSFET, it is further used to form a 6T SRAM cell. The read and write behavior of 6T SRAM cell has been studied using the read static noise margin (RSNM) and write static noise margin (WSNM). It is observed that the results obtained from the behavior of SNM show that the design of SRAM cell is more robust and highly stable. Further, the results were compared and contrasted with the reported literature, i.e., FinFET- and SOI MOSFET-based SRAM cell. The structures were designed and simulated using Synopsys TCAD device simulator.

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

An accurate method of extracting intrinsic effective mobility is proposed which considers the parasitic component and floating-body effects. The technique was verified with fabricated ultra-thin body (UTB) strained silicon-on-insulator (sSOI) MOSFETs. The accurate mobility values extracted using the newly proposed technique, were then comparatively analyzed. This novel method corrects the underestimation of mobility produced by the parasitic component and the overestimated mobility resulting from the floating-body effects.

This paper presents an experimental analysis of the influence of the silicon thickness (t si )and the channel length (L) on the threshold voltage (V t ), subthreshold swing (SS), drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL) and the ON-state over OFF-state current ratio (I ON /I OFF ))on Ultra Thin Buried Oxide (UTBOX) and Ultra Thin Body and Buried oxide (UTBB) SOI nMOSFET devices. In order to complement this analysis, a simulation of the UTBB devices was performed. Devices with thinner silicon film present better control of short channel effects resulting in improved parameters such as SS(tsi=50nm → ∼ 85–90 mV/dec; tsi=20nm → ∼ 70–80 mV/dec), DIBL(tsi=50nm → ∼ 130–150 mV/V; tsi=20nm → ∼ 25–40 mV/V), GIDL and a reduction of the channel length influence on them. When comparing the UTBB devices without and with ground plane implantation (GP) it was noted that the GP did not affect the DIBL and GIDL parameters, but it increases V t (∼0.25V without GP and ∼0.45V with GP), degrades SS and improves I on /I off (from ∼ 105 without GP to ∼108 with GP).

Huge efforts are put into CMOS scaling to push the limits of Moore’s law. Semiconductor ICs manufacturing companies are currently ramping up 16-nm/14-nm FinFET processes, with 7 and 5 nm just around the corner.

International audience; A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.

Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high C ch . Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (C DIBL ). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher C ch and C DIBL .

In this paper, we investigate the transconductance-to-current ratio (gm/ID) methods for the threshold voltage extraction using two popular threshold voltage criteria applicable to advanced bulk and SOI MOSFETs, namely: the condition of the maximum of the second derivative of the inversion charge and of the equality of the drift and diffusion drain current components. Using analytical modeling, we derive the first-order electrical parameters matching these two physical conditions and show that in the ideal MOSFET they do not coincide. The first corresponds to the point on the gm/ID versus gate voltage (Vg) curve where d(gm/ID)/dVG exhibits a minimum and where the ratio of gm/ID to its maximum value is equal to 2/3, whereas the second is met at the point where this ratio equals 1/2. The gm/ID methods for the VTH extraction using the above two criteria and their correlation with other methods are discussed. Since our modeling is based on the unified charge control model, its predictions are expected to be valid for both bulk and SOI MOSFETs. Experimental and simulation results for advanced SOI MOSFETs are used to validate modeling derivations and clarify practical applicability and limitations of the gm/ID methods.

In this paper, we present a novel physics based model for front and back gate coupling in UTBB (Ultra Thin body with Buried oxide) Fully Depleted Silicon On Insulator (FD-SOI) Transistors, which is then used in deriving the front and back gate surface potentials. To the best of our knowledge this is the first time a physical coupling model is being presented. The methodology discussed in this work is valid for any transistor irrespective of the geometry. The model shows accurate match with the exact numerical solution.

We have investigated the influence of Al0.83In0.17N barrier layer thickness (TB) on device performance of 18 nm gate length ultra thin body AlInN/GaN heterostructure underlap DG MOSFET, using 2D Sentaurus TCAD simulation. Hydrodynamic model used in the simulation is validated with previously published experimental results. Simulation of major device performance parameters such as DIBL, SS, Delay, Vt, ION and energy delay product have been done for TB ranging from 0 nm to 4 nm. A comprehensive, quantitative investigation of key analog and RF figures-of-merits such as gm, gm/Id, Ro, fT and fmax is also done. As TB increases the drain current increases and delay decreases, but at the expense of loss of electrostatic control leading to increased short channel effect i.e. higher DIBL and SS. Also, negative shift in threshold voltage is observed for rising TB. As TB reduces, increase in Cgg, gm, gm/Id and Ro is noticed due to decrease in separation between the gate and channel, leading to enhanced gate control. Improvement in both fT and fmax with reduction in TB was noticed, with the peak values of 668 GHz and 312 GHz respectively. There is tradeoff between achieved drain current, and the device electrostatic control for varying TB. Selection of appropriate TB is of vital significance as it determines the device performance.

A novel three-dimensional (3D) NAND flash memory, VCSTAR (Vertical-Channel STacked ARray), is investigated. The proposed device is a vertical channel structure having stacked word-lines to achieve high memory density without shrinking cell channel length. The VCSTAR, by using an ultra-thin body structure, can reduce the off-current level, and planar cell of VCSTAR assures insensitivity to process variables such as etch-slope. The performance of designed structure is described and the optimization of device parameter is performed by using TCAD simulation. To increase device performance and ease of fabrication, the modified fabrication method to reduce the spacing between gates is also introduced.

With the growing interest in III-V-based nano-scale transistors as potential candidates for next-generation switches there is a need for efficient simulation tools capable to predict the impact of inherent quantum effects. In this paper we show how quantum drift-diffusion (QDD) models can be used to mimic those quantum effects. The models do not only properly account for geometrical confinement in Ino.53Gao.47As FETs with a body thickness below 12 nm, but also for source-to-drain tunneling, the main cause of rising OFF-current at gate lengths shorter than 25 nm. The parameters of the QDD models available in the commercial device simulator S-Device were calibrated with the help of the quantum transport code QT-Solver. Transfer characteristics of double-gate transistors with various gate lengths were computed. Their sub-threshold swings were extracted and used as metric for the comparison. Various QDD models, also in combination with a barrier tunneling model, were tested. The pre-factor of the density-gradient model in S-Device turned out to depend on normal electric field and body thickness. Expressions for both dependencies were implemented in the Physical Model Interface of S-Device. Good agreement for inversion layer density and sub-threshold slope obtained with the QDD models and those computed with QT-Solver was found for low and high source-drain bias.

InAs ultra-thin-body (UTB) tunnel FETs (TFETs) are investigated by the sp3d5s∗ spin-on tight-binding (TB) method. We have successively implemented the reduced transformation for the TB Hamiltonian and thus highly efficient quantum-mechanical calculations based on the non-equilibrium Green's function method are made possible. Simulations of the UTB devices with body thickness up to 10nm are performed. Full quantum transport calculations by using the full TB Hamiltonian and reduced-sized mode-space Hamiltonian agree very well, while the agreement between the two depends on both the energy range for extracting the basis set and the band-to-band tunneling energy range of TFETs.

This paper presents an ultra thin body Si n-TFET which exploits a multi-finger gate layout and steep junction formed by dopant implantation into silicide (IIS) process. The sub-threshold slope (SS) reaches a minimum value of about 45 mV/dec, average SS of on /I off ratio (∼109) is achieved due to the successfully suppressed ambipolar behavior by the asymmetric source and drain design.

In this paper the influence of spacer material (S13N4, S1O2 or vacuum) on Ultra Thin Body and Buried Oxide (UTBB) SOI nMOSFET for underlapped and self-aligned drain engineering devices are studied by bi-dimensional numerical simulations. It is observed that the short length underlap devices are more influenced by spacer material. On the other hand, self-aligned does not present much spacer material dependence for the studied dimensions.

International audience; In this paper, we analyse the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra-Thin Body & BOX Fully-Depleted Silicon-on-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short defect. In addition, this work focuses on determining the individual as well as the combined improvements brought by voltage, temperature and body-biasing settings for achieving the maximum coverage of the resistive short defects.

This work presents the structure Junctionless FinFET (JLFinFET) based on ultra-thin body (UTB) with double stacked Si3N4 charge trapping layer (NN-CTL) Si-SiO2-Si3N4-Si3N4-SiO2-Si (SONNOS) nonvolatile memory (NVM). The device shows excellent transistor performances including steep sub-threshold swing (SS) of 76 mV/dec, favorable Vth, and high Ion/Ioff ratio (>107). For n-channel device, it shows excellent memory characteristics, high program/erase (P/E) performance, good endurance (>104 cycles) and an excellent 95∼99% electron retention at 85°C for 10 years.

This paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability and performance of ultra-thin-body (UTB) GeOI 6T SRAM cells integrated in monolithic 3D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. The worst case stress scenarios for read and write operations are analyzed. The optimized monolithic 3D UTB GeOI SRAM with the pulldown NFET tier stacked over the pull-up PFET tier and under forward PFET back-gate bias shows improvements in read stability and cell read-access time compared with the 2D UTB GeOI SRAM. Monolithic 3D UTB GeOI SRAM with high threshold voltage (Vth) design can enhance the improvements in stability and performance over 2D SRAM. Moreover, the optimized monolithic 3D UTB GeOI SRAM can mitigate the temporal degradations in stability and performance due to BTI stress because the BTI induced Vth degradations can be suppressed by interlayer coupling in monolithic 3D scheme.

International audience; We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

This paper investigates the impact of quantum confinement (QC) on the backgate-bias (Vbg) modulated subthreshold and threshold-voltage (Vth) characteristics of ultra-thin-body germanium-on-insulator (UTB GeOI) MOSFETs using an analytical solution of the Schrodinger equation verified with TCAD numerical simulation. Our study indicates that the QC effect reduces the sensitivity of the subthreshold swing to Vbg. In addition, the sensitivity of Vth to Vbg can be enhanced by the QC effect particularly for electrostatically well-behaved UTB MOSFETs with triangular potential well. Aside from that, the sensitivity of Vth roll-off to Vbg is reduced by the QC effect. Since Ge and Si channels exhibit different degrees of QC due to different quantization effective mass, the impact of QC has to be considered when one-to-one comparisons between GeOI and SOI MOSFETs regarding the backgate-bias modulated threshold-voltage and sub-threshold characteristics are made. Our study may provide insights for multi-Vth device/circuit designs using advanced UTB GeOI technologies.

Influence of fin width downscaling on hole and electron mobility behavior in FinFETs with (1 0 0), (1 1 0) and (1 1 1) oriented sidewalls is examined. Our effective-mass model reproduces experimental results of UTB SOI pMOSFETs fabricated on (1 0 0) and (1 1 0) surfaces, including the effect of mobility enhancement for certain body thicknesses in (1 1 0) oriented devices. The suitability of well-calibrated EMA for the simulation of hole mobility is confirmed by our results, which opens a possibility of using hole EMA in advanced Monte Carlo simulators. Simulations show that with the downscaling of fin width nFinFETs with (1 0 0) sidewalls and pFinFETs with (1 1 0) and (1 1 1) sidewalls exhibit mobility enhancement in certain fin-width ranges. In contrast, other FinFET configurations experience monotonic mobility degradation with the decreasing fin width. Regarding experimental (1 1 1) FinFETs from our previous work, modeling results suggest that the fin width is highly uniform along the channel, both in nFinFETs and pFinFETs. The impact of electron and hole mobility behavior in UTB FinFETs on SRAM design is also studied. We have found that FinFETs with (1 1 1) active surface enable the most efficient use of the layout area, demanding only four fins for an SRAM cell with matched inverters and high immunity to noise.

The high frequency performances of nano-scale ultra-thin-body (UTB) Schottky-barrier n-MOSFETs (SB-nMOSFETs) are investigated using 2D full-band self-consistent ensemble Monte Carlo method. The UTB SB-nMOSFET devices offer excellent RF performance with high values of fT and fmax. The significant dependence of fT and fmax on gate voltage and weak dependence on barrier height are demonstrated. Meanwhile, the significant dependence of gm and gds on both gate voltage and SB height are shown. Moreover, the scalability of fT is outstanding and close to the ideal case (fT ∝ 1/Lg2). The high frequency performances of 45 nm channel length SB-nMOSFETs at ballistic transport limit are also investigated. Results show that scattering strongly affects the capacitances Cgs, Cgd and Cds. At ballistic transport limit the fT and fmax are almost 10 times larger. The Scattering effects in nano-scale SB-nMOSFETs cannot be neglected.