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Reducing a set of numbers to a single value is a fundamental operation in applications such as signal processing, data compression, scientific computing, and neural networks. Accumulation, which involves summing a dataset to obtain a single result, is crucial for these tasks. Due to hardware constraints, large vectors or matrices often cannot be fully stored in memory and must be read sequentially, one item per clock cycle. For high-speed inputs, such as rapidly arriving floating-point numbers, pipelined adders are necessary to maintain performance. However, pipelining introduces multiple intermediate sums and requires delays between back-to-back datasets unless their processing is overlapped. In this paper, we present JugglePAC, a novel accumulation circuit designed to address these challenges. JugglePAC operates quickly, is area-efficient, and features a fully pipelined design. It effectively manages back-to-back variable-length datasets while consistently producing results in the correct input order. Compared to the state-of-the-art, JugglePAC achieves higher throughput and reduces area complexity, offering significant improvements in performance and efficiency., Comment: 4 pages, 1 figures, 2 tables

Fast combinational multipliers with large bit widths can occupy significant silicon area. Provided the application allows for a multiplication to last two or more clock cycles, the area can be reduced through resource sharing (i.e., folding). This work introduces multiple architectures and parameterized Verilog circuit generators for Multi-Cycle folded Integer Multiplier (MCIM) designs, which are based on Schoolbook and Karatsuba approaches. When implementing an application in hardware, it is possible that a fractional number of multiplications is performed per cycle on average, such as 3.5. In such a case, we can use 3 single-cycle multipliers plus an additional smaller multiplier with a ThroughPut (TP) of 0.5. Our MCIM designs offer customization in terms of TP, latency, and clock frequency. The MCIM idea is for a TP of $1/n$, where $n$ is an integer and $n \geq 2$. All proposed designs were synthesized and verified for various bit widths using scripts. ASIC synthesis results show that MCIM designs with a TP of 1/2 offer area savings of 21% to 48% for bit widths of 8 to 128, with respect to synthesizing the * operator. Additionally, MCIM designs can offer up to 33% energy savings and 84% average peak power reduction., Comment: 11 pages, 6 figures. Submitted to the IEEE TETC Special Section on Emerging and Impacting Trends on Computer Arithmetic

Wide Area Motion Imagery (WAMI) yields high-resolution images with a large number of extremely small objects. Target objects have large spatial displacements throughout consecutive frames. This nature of WAMI images makes object tracking and detection challenging. In this paper, we present our deep neural network-based combined object detection and tracking model, namely, Heat Map Network (HM-Net). HM-Net is significantly faster than state-of-the-art frame differencing and background subtraction-based methods, without compromising detection and tracking performances. HM-Net follows the object center-based joint detection and tracking paradigm. Simple heat map-based predictions support an unlimited number of simultaneous detections. The proposed method uses two consecutive frames and the object detection heat map obtained from the previous frame as input, which helps HM-Net monitor spatio-temporal changes between frames and keeps track of previously predicted objects. Although reuse of prior object detection heat map acts as a vital feedback-based memory element, it can lead to an unintended surge of false-positive detections. To increase the robustness of the method against false positives and to eliminate low confidence detections, HM-Net employs novel feedback filters and advanced data augmentations. HM-Net outperforms state-of-the-art WAMI moving object detection and tracking methods on the WPAFB dataset with its 96.2% F1 and 94.4% mAP detection scores while achieving a 61.8% mAP tracking score on the same dataset. This performance corresponds to an improvement of 2.1% for F1, 6.1% for mAP scores on detection, and 9.5% for mAP score on tracking over the state-of-the-art., Comment: 14 pages, 13 figures

This paper describes a graph-theoretic formalism and a flow that, to a great extent, automate the design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by Clock Tree Synthesis (CTS) software. In spite of critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. We exploited these similarities and built a design flow and tool set, which uses commercial digital CTS software as an intermediate step. We will explain our flow using a 0.18 micron 10-bit 60 MHz 2-stage pipelined differential-input flash analog-to-digital converter as a test circuit., Comment: 12 pages, 24 figures, 2 tables

Neural network deployment on low-cost embedded systems, hence on microcontrollers (MCUs), has recently been attracting more attention than ever. Since MCUs have limited memory capacity as well as limited compute-speed, it is critical that we employ model compression, which reduces both memory and compute-speed requirements. In this paper, we add model compression, specifically Deep Compression, and further optimize Unlu's earlier work on arXiv, which efficiently deploys PyTorch models on MCUs. First, we prune the weights in convolutional and fully connected layers. Secondly, the remaining weights and activations are quantized to 8-bit integers from 32-bit floating-point. Finally, forward pass functions are compressed using special data structures for sparse matrices, which store only nonzero weights (without impacting performance and accuracy). In the case of the LeNet-5 model, the memory footprint was reduced by 12.45x, and the inference speed was boosted by 2.57x., Comment: 7 pages, 1 figure