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285 results on '"Ubar, R."'

1. New categories of Safe Faults in a processor-based Embedded System

Author

Gursoy, C. C., Jenihhin, M., Oyeniran, A. S., Piumatti, D., Raik, J., Reorda, M. Sonza, and Ubar, R.

Subjects
Computer Science - Hardware Architecture
Abstract

The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor., Comment: 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Published
2020
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2. Evolutionary Approach to Test Generation for Functional BIST

Author

Skobtsov, Y. A., Ivanov, D. E., Skobtsov, V. Y., Ubar, R., and Raik, J.

Subjects
Computer Science - Neural and Evolutionary Computing
Abstract

In the paper, an evolutionary approach to test generation for functional BIST is considered. The aim of the proposed scheme is to minimize the test data volume by allowing the device's microprogram to test its logic, providing an observation structure to the system, and generating appropriate test data for the given architecture. Two methods of deriving a deterministic test set at functional level are suggested. The first method is based on the classical genetic algorithm with binary and arithmetic crossover and mutation operators. The second one uses genetic programming, where test is represented as a sequence of microoperations. In the latter case, we apply two-point crossover based on exchanging test subsequences and mutation implemented as random replacement of microoperations or operands. Experimental data of the program realization showing the efficiency of the proposed methods are presented., Comment: 10 European Test Symposium. Informal Digest of Papers

Published
2010

4. An Approach to System-level Design for Test

Author

Jervan, G., Ubar, R., Peng, Z., Eles, P., Itoh, Kiyoo, editor, Lee, Thomas, editor, Sakurai, Takayasu, editor, Sansen, Willy M. C., editor, Schmitt-Landsiedel, Doris, editor, Sonza Reorda, Matteo, editor, Peng, Zebo, editor, and Violante, Massimo, editor

Published
2005
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5. Test Generation: A Hierarchical Approach

Author

Jervan, G., Ubar, R., Peng, Z., Eles, P., Itoh, Kiyoo, editor, Lee, Thomas, editor, Sakurai, Takayasu, editor, Sansen, Willy M. C., editor, Schmitt-Landsiedel, Doris, editor, Sonza Reorda, Matteo, editor, Peng, Zebo, editor, and Violante, Massimo, editor

Published
2005
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22. Turbo Tester – diagnostic package for research and training

Author

AARNA M., IVASK E., JUTMAN A., ORASSON E., RAIK J., UBAR R., VISLOGUBOV V., and WUTTKE H.-D.

Abstract

This paper describes a diagnostic software package called Turbo Tester. It contains a variety of tools related to the area of testing and diagnosis of integrated circuits. The range of tools includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, built-in self-test simulators, design verification and design error diagnosis tools. The range of compatible diagnostic tools forms, via their interaction and complementary operation, a homogeneous research environment, which provides good possibilities for experimental research. Due to this fact, there are a number of scientific papers became possible. These papers have been presented at international conferences and published in reviewed journals. We give a couple of examples of such experiments in this paper. We also describe some laboratory work scenarios for students.

Published
2003

27. High-level decision diagrams for improving simulation performance of digital systems

Author

Ubar, R., Morawiec, A., Raik, J., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Tallinn Technical University, Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
PACS 8542, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Decision diagrams (DD) present a suitable way for the digital system representation efficiently used in several steps of the entire design cycle : design verification, testing, test pattern generation and fault simulation. This paper presents some ways to optimize the decision diagram representation aimed at improving simulation efficiency. Two new types of diagrams are introduced : vector decision diagrams (VDDs) and compressed VDDs, as an efficient and concise model of the system behavior, which preserves all the advantes of the decision diagrams. In order to fully exploit the advantages of DDs new simulatioan algorithms based on cycle-based forward event-driven and recursive back-tracing techniques are proposed. The experimental results of the comparison of different types of DDs as well as of different simulation algorithms on DDs are included.

Published
2000

28. Vector decision diagrams for simulation of digital systems

Author

Ubar, R., Morawiec, A., Raik, J., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Tallinn Technical University, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), and Torella, Lucie

Subjects
PACS 8542, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Decision diagrams (DD) present a suitable way for the digital system representation efficiently used in several steps of the entire design cycle : for design verification, test generation and fault simulation. They offer a competitive simulation performance in comparison to the event-driven HDL-based simulation ; however, their initial complexity does not allow to favorably compare their performance with the algorithmic functional description of the circuit's behavior. This article presents the optimization of the DD representation aimed at improving their simulation efficiency. Two types of DDs are introduced : vector decision diagrams (VDDs) and compressed VDDs as an efficient and concise model of system behavior, which preserves all the advantages of the decision diagrams. Their computational complexity is similar to the algorithmic description. The results of the comparisons between the different types of DDs and the algorithmic representation are included. This comparison is based on the symbolic complexity measure, defined for that purpose.

Published
2000

29. Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

Author

Leveugle, R., Ubar, R., Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), CSI, Inst. Nat. Polytech. de Grenoble, France (CSI), Institut National Polytechnique de Grenoble (INPG), Tallinn Technical University, Torella, Lucie, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
collapsing-faults, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, low-level-implementation-details, hierarchical-test-synthesis, decision-diagrams-synthesis, model-compression, GeneralLiterature_MISCELLANEOUS, PACS 8542, ATPG, functional-test-generation, PACS 85.42, clock-driven-multi-process-VHDL-descriptions, DD-superposition, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

A method is presented for creating decision diagrams (DD) from multi-process VHDL descriptions for test generation purposes. Each process in the VHDL description will be represented either by one or several DDs. To increase the efficiency of test generation, a method is given for compressing the model and collapsing faults by superposition of DDs. The method supports well functional test generation as well as hierarchical test synthesis if the low level implementation details can be provided. Experimental results are included to show the efficiency of using DDs in test generation.

Published
1999

30. Single gate design error diagnosis in combinational circuits

Author

Ubar, R., Borrione, D., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
single-gate-design-errors, hierarchical-approach, decision-diagrams, combinational-circuits, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, standard-gate-level-ATPG, stuck-at-fault-model, Hardware_PERFORMANCEANDRELIABILITY, single-gate-design-error-diagnosis, fault-simulation, PACS 85.42, tree-like-subcircuit, macro-level-test-generation, verification, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, faulty-macro
Abstract

INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 1406-0175; We propose a new approach to generate diagnostic tests and localize single gate design errors in combinational circuits. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level automated test pattern generators for verification and design error diagnosis purposes. A powerful hierarchical approach is proposed for generating test patterns which, at first, localize the faulty macro (tree-like subcircuit), and then localize the erroneous gate in the faulty macro. Experimental data show the efficiency of the macro-level test generation and fault simulation compared to the plain gate-level approaches.

Published
1999

34. Compaction of decision diagrams for describing multi-process VHDL descriptions

Author

Leveugle, Régis, Saucier, G., Ubar, R., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), CSI, INPG, Grenoble (CSI), Institut National Polytechnique de Grenoble (INPG), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), and Torella, Lucie

Subjects
compressed-DDs, decision-diagrams, functional-test-generation, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fine-grained-timing-model, PACS 85.42, multi-process-VHDL-descriptions, test-generation-complexity, decision-diagram-compaction, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, coarse-timing-model, test-generation-efficiency
Abstract

ISBN: 9985590813; A method is presented for compressing decision diagrams (DD) created for multi-process VHDL descriptions with the goal of functional test generation. Each process is represented either by one DD or a set of DDs. The fine-grained timing model is replaced by a coarse timing model which helps to reduce the complexity of test generation. A set of rules for compressing the DD model is given. The method is illustrated by example. Experimental data to prove the efficiency of test generation based on compressed DDs is presented.

Published
1998

36. Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults

Author

Ubar, R., Borrione, D., Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
PACS 8542, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, diagnosis of complex systems, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Hardware_LOGICDESIGN
Abstract

International audience; A new approach to detecting and localizing single gate design errors in combinational circuits is proposed. The method is based on using fault tables for stuck-at fault diagnosis with subsequent translation of the result into the design error area. This allows to exploit standard gate-level ATPGs also for diagnosis of design errors. A powerful hierarchical approach is proposed based on using structurally synthetized BDDs, where combining the error detection and diagnosis phases into a single whole allows to drastically reduce the amount of work for error site localization.

Published
1998

38. Test time minimization for hybrid BIST of core-based systems

Author

Jervan, Gert, Eles, Petru Ion, Peng, Zebo, Ubar, R., Jenihhin, M., Jervan, Gert, Eles, Petru Ion, Peng, Zebo, Ubar, R., and Jenihhin, M.

Abstract

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. © Springer Science + Business Media, Inc. 2006.

Published
2006
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40. A benchmark suite for evaluating the efficiency of test tools

Author

Kruus, H., primary, Ubar, R., additional, Ellervee, P., additional, Gorev, M., additional, Pesonen, V., additional, Devadze, S., additional, Orasson, E., additional, Brik, M., additional, Min, M., additional, Annus, P., additional, Kruus, M., additional, and Meigas, K., additional

Published
2012
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41. RT-level test point insertion for sequential circuits

Author

Raik, J., Govind, Vineeth, Ubar, R., Raik, J., Govind, Vineeth, and Ubar, R.

Abstract

Current paper presents a new, coarse-grain method for test point insertion performed at the RT-level The method relies on inserting testability components to the RTL VHDL description of the design. The approach is based on non-classical, simplified concept of controllability and observability. The insertion takes place based on the list of uncontrollable and unobservable faults obtained by a sequential ATPG. Such interaction with an ATPG and resynthesis of the device after each test structure insertion would be very time-consuming. The proposed method solves its task with just three iterations. First, a testability analysis is carried out and controllability structures are inserted to the modules containing uncontrollable faults. Then, the circuit is resynthesized and the ATPG is run. Second, the observability structures are added to the modules, with remaining unobservable faults. Finally, after resynthesis and an ATPG run the overhead area is minimized by removing observability structures from blocks, where there was no increase in fault coverage. A synthesizable VHDL library of dedicated generic components for testability structures has been implemented. Experiments on six RTL benchmarks show the efficiency of the approach., QC 20141212

Published
2004

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