Search

We demonstrate tunable bistability and a strong negative differential resistance in InAs/GaSb core-shell nanowire devices embedding a radial broken-gap heterojunction. Nanostructures have been grown using a catalyst-free synthesis on a Si substrate. Current-voltage characteristics display a top peak-to-valley ratio of 4.8 at 4.2 K and 2.2 at room temperature. The Esaki effect can be modulated - or even completely quenched - by field effect, by controlling the band bending profile along the azimuthal angle of the radial heterostructure. Hysteretic behavior is also observed in the presence of a suitable resistive load. Our results indicate that high-quality broken-gap devices can be obtained using Au-free growth.

In this article, we compare the excitation wavelength dependence of the polarization anisotropy (ρ) of an internal field induced Raman scattering signal in individual bare InAs and InAs/GaSb core-shell nanowires. The measured value of ρ of the Raman scattering intensity for InAs/GaSb core-shell nanowires has a minimum at ∼500 nm, while for the bare InAs nanowire, the value of ρ monotonically increases over the same range of wavelengths. We have modeled the scattering intensities of both systems by considering the joint role of Raman tensor components and confinement of electromagnetic radiation inside the nanowire at two orthogonal polarization configurations of the electromagnetic radiation. The theoretical results allow us to understand that the observed behavior of ρ is related to the nanowire geometry and to the difference in the wavelength dependence of the dielectric constants of InAs and GaSb. This work shows the possibility of manipulating the polarization anisotropy by selecting suitable diameters and materials for the core and the shell of the nanowire. We also report a six-fold increase in Raman scattering intensity due to the GaSb shell on InAs nanowires.In this article, we compare the excitation wavelength dependence of the polarization anisotropy (ρ) of an internal field induced Raman scattering signal in individual bare InAs and InAs/GaSb core-shell nanowires. The measured value of ρ of the Raman scattering intensity for InAs/GaSb core-shell nanowires has a minimum at ∼500 nm, while for the bare InAs nanowire, the value of ρ monotonically increases over the same range of wavelengths. We have modeled the scattering intensities of both systems by considering the joint role of Raman tensor components and confinement of electromagnetic radiation inside the nanowire at two orthogonal polarization configurations of the electromagnetic radiation. The theoretical results allow us to understand that the observed behavior of ρ is related to the nanowire geometry and to the difference in the wavelength dependence of the dielectric constants of InAs and GaSb. This work shows the possibility of manipulating the polarization anisotropy by selecting suitable diameter...

A comparative assessment of AlGaN/GaN high-electron-mobility transistors (HEMTs) grown by molecular beam epitaxy on silicon and sapphire substrates has been carried out. Large-area power GaN HEMTs with identical device dimensions were fabricated on both substrates. A thicker AlN buffer layer was used for the GaN HEMT on silicon to achieve similar quality and uniformity of GaN epitaxy for rational comparison with that grown on sapphire. Direct-current analysis and physical characterization were carried out to understand the performance of the devices. Mathematical measurement of the instability of the current–voltage (I–V) characteristic at high applied drain bias was carried out to evaluate the performance of both devices. An improved two-dimensional (2D) analysis of the I–V characteristic was performed from a thermal perspective including appropriate scattering effects on the 2D electron gas mobility. The experimental and analytical studies were correlated to reveal the effects of temperature-sensitive scattering phenomena on the mobility as well as on the I–V characteristic at high drain bias in terms of lattice thermal heating. It is observed that the HEMT on Si has improved stability compared with sapphire due to its weaker scattering phenomena at high drain bias, associated with its thermal conductivity. Simulation of 2D thermal mapping was also carried out to distinguish the hot-spot regions of the devices. The comparable electrical performance of these devices illustrates the viability of AlGaN/GaN HEMTs on Si(111) to achieve low-cost stable devices with better thermal power handling for high-voltage applications.

The performance of InAlAs/InGaAs quantum well field effect transistors are subject to high impact ionization and band-to-band tunneling (BTBT) due to its narrow bandgap feature. In this work, the energy gap is engineered using strain and quantization techniques to increase the effective energy gap leading to low impact ionization and BTBT leakage current. It is shown that the impact ionization is reduced in 5 nm channel device as compared to 13 nm device with onset at approximately Egeff/q. Also the band-to-band-tunneling current is reduced due to the increase in effective energy gap. We have also investigated the effects of quantum well engineering on the dc performance of InGaAs HEMTs.

We report on the nucleation and growth mechanism of self-catalyzed InAs nanowires (NWs) grown on Si (111) substrates by chemical beam epitaxy. Careful choices of the growth parameters lead to In-rich conditions such that the InAs NWs nucleate from an In droplet and grow by the vapor-liquid-solid mechanism while sustaining an In droplet at the tip. As the growth progresses, new NWs continue to nucleate on the Si (111) surface causing a spread in the NW size distribution. The observed behavior in NW nucleation and growth is described within a suitable existing theoretical model allowing us to extract relevant growth parameters. We argue that these results provide useful guidelines to rationally control the growth of self-catalyzed InAs NWs for various applications.

Au-catalyzed III-V nanowire heterostructures based on the group III interchange usually grow straight only in one of the two growth sequences, whereas the other sequence produces kinked geometries; thus, the realization of double heterostructures remains challenging. Here, we investigate the growth of Au-assisted InAs-GaAs and GaAs-InAs axial nanowire heterostructures. A detailed study of the heterostructure morphology as a function of growth parameters and chemical composition of the catalyst nanoparticle is performed by means of scanning electron microscopy, transmission electron microscopy, and energy-dispersive X-ray analysis. Our results clearly demonstrate that the nanoparticle composition, rather than other growth parameters, as postulated so far, controls the growth mode and the resulting nanowire morphology. Although GaAs easily grows straight on InAs, straight growth of InAs on GaAs is achieved only if the nanoparticle composition is properly tuned. We find that straight InAs segments on GaAs require high group III-to-Au ratios in the nanoparticle (greater than 0.8); otherwise, the droplet wets the sidewalls and the nanowire kinks. We discuss the observed behavior within a theoretical model that relates the nanoparticle stability to the group III-to-Au ratio. Based on this finding, we demonstrate the growth of straight nanowire heterostructures for both sequences. The proposed strategy can be extended to other III-V nanowire heterostructures based on the group III interchange, allowing for straight morphology regardless of the growth sequence, and ultimately for designing nanowire heterostructures with the required properties for different applications.

A review is presented on the advances in InAlAs/InGaAs High Electron Mobility transistors (HEMT) on silicon substrates for high frequency and low noise applications. Although InAlAs/InGaAs HEMTs on InP and GaAs substrates have been much appreciated due to their superior performance, their widespread applications have been hindered due to higher cost of the substrates. Silicon has been used as an alternative substrate considering the benefits of low cost, technological maturity and integration of III-V and silicon technology inspite of the constraints like lattice mismatch and large difference in thermal expansion coefficient.

In this paper the strain effects on the performance and reliability of future digital III-V device are discussed. Strain is incorporated in the device during fabrication, packaging, and operation. A high amount of strain can introduce defects and cracks in the epilayer. The band structure of the active device region is also altered due to strain. These strain induced changes determine performance, reliability, and lifetime of the device. Therefore, it is necessary to consider strain effects while designing a device for a particular application. Here, compressive-strain-induced changes are used as design parameters and their impact on the logic performance of the device is studied. It is interpreted that the design significantly decreases the gate leakage current and improves the subthreshold slope.

We investigate a growth mechanism which allows for the fabrication of catalyst-free InAs nanowires on Si (111) substrates by chemical beam epitaxy. Our growth protocol consists of successive low-temperature (LT) nucleation and high-temperature growth steps. This method produces non-tapered InAs nanowires with controllable length and diameter. We show that InAs nanowires evolve from the islands formed during the LT nucleation step and grow truly catalyst-free, without any indium droplets at the tip. The impact of different growth parameters on the nanowire morphology is presented. In particular, good control over nanowire aspect ratio is demonstrated. A better understanding of the growth process is obtained through the development of a theoretical model combining the diffusion-induced growth scenario with some specific features of the catalyst-free growth mechanism, along with the analysis of the V/III flow ratio influencing material incorporation. As a result, we perform a full mapping of the nanowire morphology versus growth parameters which provides useful general guidelines on the self-induced formation of III-V nanowires on silicon.

We report on the heterogeneous nucleation of catalyst-free InAs nanowires on Si (111) substrates by chemical beam epitaxy. We show that nanowire nucleation is enhanced by sputtering the silicon substrate with energetic particles. We argue that particle bombardment introduces lattice defects on the silicon surface that serve as preferential nucleation sites. The formation of these nucleation sites can be controlled by the sputtering parameters, allowing the control of nanowire density in a wide range. Nanowire nucleation is accompanied by unwanted parasitic islands, but by careful choice of annealing and growth temperature allows to strongly reduce the relative density of these islands and to realize samples with high nanowire yield.

We present experimental data on the length distributions of InAs nanowires grown by chemical beam epitaxy with Au catalyst nanoparticles obtained by thermal dewetting of Au film, Au colloidal nanoparticles and In droplets. Poissonian length distributions are observed in the first case. Au colloidal nanoparticles produce broader and asymmetric length distributions of InAs nanowires. However, the distributions can be strongly narrowed by removing the high temperature annealing step. The length distributions for the In-catalyzed growth are instead very broad. We develop a generic model that is capable of describing the observed behaviors by accounting for both the incubation time for nanowire growth and secondary nucleation of In droplets. These results allow us to formulate some general recipes for obtaining more uniform length distributions of III-V nanowires.

The performance of GaN/InGaN quantum well was simulated using ATLAS software (Silvaco International Inc.) In this work, we simulated a quantum well active region of InGaN with GaN barrier layers. Here, we studied the changes in luminous intensity by varying thickness of the well region and Indium mole fraction of InGaN quantum well. It is found that the luminous intensity decreased when the thickness of the active layer was increased. It is also observed that luminous intensity increased with increasing Indium mole fraction up to 10% but decreased after this. An optimum result was observed at mole fraction constant of 0.175 for 2 nm well width and 6 nm barrier width.

III-V semiconductor nanowires have attracted intensive research interest because of their promising optical and electronic properties that can be manipulated by tailoring nanowire composition and morphology. Therefore, it is crucial to measure and control the diameter distribution of the grown nanowires. In this study, we analyze the diameter distribution of Au-catalyzed InAs nanowires. Au colloidal nanoparticles dispersed on InAs (111) B substrates and nanoparticles obtained by the thermal annealing of Au films were used as catalysts for InAs nanowire growth. The annealing time and temperature, the thickness of the Au film and the colloid sizes were systematically varied not only to understand their influence on nanowire diameter distribution, but also to find the optimal parameters for realizing samples with uniform and controlled diameter distribution. Morphological characterization was performed by scanning electron microscopy measurements and the image analysis was carried out using in-house-developed automated image analysis software to accurately determine the diameter distribution of the nanowires. A description of the image analysis software is also presented. The thermal annealing of films turned out to be the most suitable method for uniformity and density control, while the colloidal nanoparticles yielded narrow and more reproducible diameter distributions.

InxAl1-xN/AlN/GaN HEMT device performance is analysed at various temperatures with the help of physics based 2-D simulation using commercially available BLAZE and GIGA modules from SILVACO. Various material parameters viz. band-gap, low field mobility, density of states, velocity saturation, and substrate thermal conductivity are considered as critical parameters for predicting temperature effect in InxAl1-xN/AlN/GaN HEMT. Reduction in drain current and transconductance has been observed due to the decrease of 2-DEG mobility and effective electron velocity with the increase in temperature. Degradation in cut-off frequency follows the transconductance profile as variation in gate-source/gate-drain capacitances observed very small.

In this work, by means physics based drift-diffusion simulations, three different narrow band gap semiconductors; InAs, InSb and In0.53Ga0.47As, and their associated heterostructures have been studied for future high speed and low power logic applications. It is observed that In0.53Ga0.47As has higher immunity towards short channel effects with low DIBL and sub-threshold slope than InSb and InAs. Also it is observed that for the same device geometry InSb has the highest drive current and lower intrinsic delay but its ION/IOFF figure of merit is deteriorated due to excess leakage current. 1. Introduction The narrow bandgap III-V semiconductors (InAs, InSb and In0.53Ga0.47As) have attracted considerable attention as alternative channel materials for beyond silicon logic applications due to their very high electron mobility and saturation velocity. The superior electronic properties of III-V materials translate to favorable logic figure of merits for ultra high-speed and low-power logic applications. This paper endeavors to predict the logic performance of these next-generation digital III-V family materials and present a comparative analysis using physics based two-dimensional drift-diffusion simulator. For the first time in order to investigate the potential of these materials for digital applications they are introduced into the channel of their associated heterostructure devices of similar geometry. 2. Device Structure and Model Reliability of device modelling is based on accurate physical models and material parameters which are not completely available in the simulator database. As a prerequisite for simulation of devices based on III-V compound semiconductors, material parameters have been obtained through bibliographic review. The physical material parameters for the ternary alloys are obtained from experimental data and vegard's interpolation schemes from generally accepted values for the binary compounds. Figure 1 shows the vertical band profile of the devices under study. These structures are designed to evaluate the digital performance of specific channel materials and to bring forward an effective comparison. Therefore for the first time the transistors with different channels are modeled with same device geometry. In order to rationale that gate leakage is mostly due to material properties the heterojunctions have type I configuration which confines the holes in the channel and minimizes leakage current (1). The structures consist of a 10 nm narrow bandgap channel sandwiched between a 4 nm, high bandgap barrier layer and a 0.16 μm thick buffer layer. The device that employs InAs as the primary channel is inserted between In0.53Ga0.47As sub-channels to realize the lattice-match criteria. Channel charge is supplied through a delta-doped layer at a concentration of 3×10 12 cm -2 located in the barrier just below the gate and a spacer layer of 5 nm separates the channel from the barrier to prevent scattering of electrons. The gate length of the devices is 40 nm and gate-source/drain