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A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

In this research, an n-type metal-oxide-semiconductor field effect transistor (nMOSFET) device with a SiGe channel exerted by the combination of a contact etching stop layer (CESL) and silicon germanium (Si1-xGe(x)) channel stressors is proposed. To explore the foregoing mechanical effect on the stress distribution of nMOSFETs within the channel region, a process-oriented simulated technique is adopted for the concerned nMOSFET device. The loading sources are a 1.1 GPa tensile CESL (t-CESL) and a SiGe channel structure constructed with 0%, 22.5%, and 25%, germanium (Ge) mole fractions. The results of the simulation show that the stress components of the Si1-xGe(x) channel evidently increase when the Ge mole fraction within a Si1-xGe(x) layer is increased. A pulling force exerted on the protruding gate structure by the CESL layer that causes dominant bending deformation and channel stress variation behaviors is a major reason for this phenomenon. Therefore, the degree of bending effect caused by the protruding gate structure is concluded as being the key to determining the trends and stress magnitudes of the Si1-xGe(x) device channel.

In this research, an n-type metal-oxide-semiconductor field effect transistor (nMOSFET) device with a SiGe channel exerted by the combination of a contact etching stop layer (CESL) and silicon germanium (Si1-xGe(x)) channel stressors is proposed. To explore the foregoing mechanical effect on the stress distribution of nMOSFETs within the channel region, a process-oriented simulated technique is adopted for the concerned nMOSFET device. The loading sources are a 1.1 GPa tensile CESL (t-CESL) and a SiGe channel structure constructed with 0%, 22.5%, and 25%, germanium (Ge) mole fractions. The results of the simulation show that the stress components of the Si1-xGe(x) channel evidently increase when the Ge mole fraction within a Si1-xGe(x) layer is increased. A pulling force exerted on the protruding gate structure by the CESL layer that causes dominant bending deformation and channel stress variation behaviors is a major reason for this phenomenon. Therefore, the degree of bending effect caused by the protruding gate structure is concluded as being the key to determining the trends and stress magnitudes of the Si1-xGe(x) device channel.

A robust finite element analysis (FEA) is beneficial to quality the microbump assembly by using process-flow technique and to estimate subsequent thermo-mechanical reliability of critical microbump in a whole 3D-ICs packaging structure. However, the foregoing simulation work is time-consuming and becomes difficult to obtain a converged numerical result while thousands of microbumps with an array-type need to be taken into account simultaneously. For this reason, this research proposed a simulated technique to introduce an equivalent material composed of microbumps and their surrounding underfill. The mechanical properties of above-mentioned equivalent material, including Young's modulus, Poisson's ratio, and coefficient of thermal extension are directly obtained applying a tensile load and giving a increment in temperature during FEA, respectively. The analytic results indicate that at least five microbumps at the outermost region of chip stacking structure need to be considered as an accurate stress/strain contour in concerned region is achieved.

Fatigue behavior with an extreme flexural stress loaded on OLED devices has been greatly paid attention while the packaging structure having multi-stacked films becomes thinner and more flexible. To reduce mechanical impact and enhance reliability for OLED and related critical film materials, a derived mechanical model of plural layers is presented. Moreover, a nonlinear finite element analysis combined with the approach of full factorial design is performed to explore several concerned mechanical parameters within a whole structure. The results reveal that the thickness of PI_substrate is the most dominant to determine the position of neutral axis and the bending stress of indium tin oxide film, separately. It is also found that all the significances of main effects for each factor are obviously larger than the interaction effect among them. Consequently, the use of either thinner film or softer constitute for each layer could be able to reduce ITO stress effectively.