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Chemical-mechanical polishing closed loop control optimized process with machine learning assisted wafer image analysis algorithm implemented on the inter layer dielectric of 3D NAND ON stacking with poly-silicon stop layer is studied. The grayscale wafer image can be responded for film residue, stop layer damage, wafer edge damage, and thickness variation. Polishing five zones control model is trainned with wafer grayscale value by Python NN model with two hidden layers. The best condition of closed loop feedback control is deduced by machine learning assisted wafer image analysis algorithm.

Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. Furthermore, slurries or other consumable parts, like PAD and Disks selection are also the keys for CMP process optimization. The most difficult thing in CMP process is to have capability to predict and cover the various topologies and layout densities patterned wafers and preventing the hot spots occurrences. In this study, different Neural-Network algorithm with data pre-processing models are implemented to the in-line CMP CLC tuning and dishing/erosion prediction at various topology/pattern density test vehicle pattern wafers. Transfer learning technique is implemented on the original Neural -Network algorithm model, the behavior of real product can be simulated and predicted based on the knowledge of test vehicle database successfully. With the aid of multiple layer erosion/ dishing Neural-Network algorithm model prediction, the potential high risky hot spots can be highlighted at the initial layout design stage, then further shorten the turn-around time of design layout validation.

Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties; different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development.

Serious tungsten corrosion after tungsten chemical mechanical planarization (W CMP) is found to correlate to the high via resistance. According to via design layout analysis, the W plug recess is strongly dependent on the underlying metal line area and via hole size. The via W plug recess becomes worse as via size shrinkage and underlying metal line area increasing. The low corrosion W polishing slurry, alkali /acidic buffing slurry and clean chemical are studied. The result indicates that low corrosion W slurry and acidic clean chemical can suppress tungsten corrosion and result in tightened via resistance distribution in 1× nm device product.

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn’t directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

The defect inspection results for advanced technology nodes have extremely high defect counts frequently. Therefore, the defect review Pareto get high false rate due to the SEM non-visual defects, nuisance defects, or dummy fill patterns by traditional review sampling methodology. An integrated smart review sampling methodology is proposed to resolve the high false rate issue and dig out the DOIs and POIs effectively in huge big inspection results with aid of design data base.

As device rule shrinks, the finding of systematic hot spots is no longer just relied on design rule checking (DRC) and lithography rule checking (LRC). There still have some unexpected systematic hot spots impact the yield of production. Using image contour extraction technique to extract the images of issued failure sites into unit clipped patterns and then do the patterns search with a similarity algorithm. Transfer these specific pattern search care areas into an in-line inspection recipe, and then prevent the failure issues happening again. Through regrouping the seed patterns after hot scan on focus exposure matrix (FEM) or process window qualification (PWQ) wafers, the exactly or similar pattern search of these seed patterns can help us to find out the unknown risky similar pattern of interests.

The inspection strategy and technique of high aspect ratio contact modules are demonstrated in this paper. Pre-scan with dark or bright field inspection then reviewing by Vcap condition at contact opening layer is to confirm the HAR contact patterning performance. e beam inspection with feasible conditions right after plug CMP is to monitor the whole contact module and the plugs fill-in performance.

Process window simulation results are implemented into a yield drop case induced by ILD contact module process shift. Signatures of blind voltage contrast and ILD thickness variation coincide with failure map of wafer sort. Lower down the edge pressure of ILD CMP and increase the O2 flow ratio in BPSG SACVD process can well-control the ILD CMP thickness variation within 500A, and get more uniform dopant distribution in ILD layer. Yield is back to normal after processes optimization.

The inspection sensitivities and capture rate capabilities of high resolution e-beam inspection system with extracting and retarding mode are evaluated. E-beam with retarding mode inspection demonstrates better performance and reflects the wafer sort yield loss in contact failure items directly. After the contact module process optimization, the yield was improved almost two times above.

High resolution e-beam review system with critical point inspection (CPI) function is implemented to verify the systematic defects in both array and periphery area of NOR Flash products. CPI inspection can help us to intercept with unobvious systematic defects and find the process variation to save the cost of yield loss from time to time, and it is important for debugging the systematic defects in irregularly periphery circuits.

This paper applied a grain-refinement technique to develop an alternative poly-silicon floating gate. Micro-grain poly-silicon grains were refined by using a single-wafer LPCVD processor and adding hydrogen. The SIMS analysis of micro-grain poly-silicon films revealed that hydrogen contributed to poly-silicon formation but was not incorporated into the poly-silicon films. The grain size and dopant concentration of poly-silicon affected oxide integrity. The grain size of micro-grain poly-silicon was well controlled under 15 nm by annealing with 950°C /30s N2. A 100 k-cycle erase-program endurance test of a single-wafer LPCVD processor confirmed that the micro-grain floating gate poly-silicon with hydrogen had better endurance compared to conventional furnace poly-silicon.

Sequential flow chemical vapor deposition (SFCVD), utilizing TiCl 4 /NH 3 as reactants and immediate NH 3 treatment after film deposition, is applied to produce TiN barrier films in the contact process. Secondary ion mass spectroscopy results indicate that the SFCVD TiN film can effectively block the diffusion of WF 6 into the underlying Ti layer during W deposition. NH 3 treatment immediately after film deposition causes SFCVD TiN films to be less contaminated with carbon than TiN films that are formed by metallic organic compounds chemical vapor deposition (MOCVD) and to contain less chlorine residue than conventional TiCl 4 /NH 3 CVD TiN layers even at a low reaction temperature. According to the resistance measurement of Kelvin contacts, the SFCVD process yields a lower resistance and a more uniform distribution than the MOCVD or CVD process. Transmission electron microscopic observations demonstrate that WF 6 can diffuse through the MOCVD TiN to react with the underlying Ti layer, causing a rupture at the Ti/TiN interface and poor W adhesion. The SFCVD TiN can serve as a sufficient diffusion barrier against WF 6 penetration during W CVD deposition.

This study investigates inter-metal dielectric (IMD) layer with a perhydro-polysilazane-based inorganic spin-on-glass (PSZ–SOG) dielectric layer in 100 nm node multilevel metallization technology. When the PSZ–SOG film is cured in N2 ambient, the via resistance is worsened; the via resistance declines as the number of wafers in sequence increases because the SOG film tends to adsorb a large amount of moisture and forms a porous IMD film structure. However, when it is cured in O2 ambient, optimization by via adhesion degassing can minimize the slot effect and yield good via resistance. In this study, the non-etchback PSZ–SOG process is integrated by using 100 nm multilevel metallization technology without an expensive high density plasma chemical vapor deposition (HDP CVD) oxide process or modification of design rules. After the SOG curing recipe and degassing condition in the via adhesion film deposition have been optimized, the PSZ–SOG exhibits excellent planarization, a dense IMD structure and good via resistance performance that is comparable with that of the traditional HDP CVD oxide process.

A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure.

This investigation elucidates various tungsten (W) nucleation layers in different W-plug fill processes. Four W-plug nucleation layers are evaluated. They involve an atomic layer deposition (ALD) W nucleation with SiH"4-base sequential nucleation layers, an ALD W nucleation with B"2H"6-base sequential nucleation layers, a conventional W chemical vapor deposition (CVD) nucleation layer, and a pulsed nucleation layer, respectively. Bulk deposition includes high pressures of 300Torr and conventionally 90Torr with hydrogen as a reductant of WF"6. A scanning electron microscopic analysis of the ALD W nucleation layer is conducted; it is a thin, smooth and dense film, which enhances the bulk deposition grain growth to increase grain size with low resistivity. Electrical results for ALD W processes are comparable to those for conventional W process in general barrier process condition. However, as the W-plug fills process on the weak and thin metal organic chemical vapor deposited (MOCVD) TiN barrier is varied, the ALD W processes retain their original electrical resistance performance. Unlike ALD W processes, the conventional W CVD suffers from serious contact resistance opening and tail bits. Transmission electron microscope profiles reveal that the thin and dense B"2H"6-base sequential nucleation layers prevent WF"6 molecular penetration through the TiN/Ti"x interface. Additionally, various W-plug fill processes are implemented in the tungsten damascene test vehicle, and the ALD B"2H"6-base sequential nucleation layers and subsequently formed bulk deposition at 300Torr have lower resistance than under other conditions. The contact profile obtained using the transmission electron microscope reveals that the ALD B"2H"6-base W-plug has favorable fill-in capability for both 100nm and 60nm contact sizes. Their lower resistivity and thinner nucleation layer suit them in particular to implement at a contact size of 100nm and smaller. The ALD B"2H"6-base sequential nucleation layers and subsequently formed bulk deposition at 300Torr can be used in the next generation of W-plug fill process.

Generally CD (critical dimension) measurement is an important role for verify the FEM (Focus Exposure Matrix) process window. However, the generally CD measurement is rough due to only measure few site in wafer. The results cannot get the high accuracy information for verification the FEM process window and waste a lot of FEM process time. In this paper, we have demonstrate a new methodology that can get rapidly and precisely verify FEM process window by advanced CD measurement go through high resolution images and contour extraction.

Color abnormal phenomenon in post Cu chemical mechanical planarization (CMP) is found in 3X nm flash memory. TEM cross-section shows that there is no Cu residue but has localized thickness variation. This color abnormal phenomenon cannot be eliminated with subsequently Cu and barrier polishing. According to experimental results, the non-uniform inhibitor distribution of Cu slurry issue will enhance the localized Cu dishing profile and lead to thickness variations after barrier polishing. This phenomenon is found especially at high selectivity Cu slurry in advanced Cu CMP process. Color abnormal issue is resolved by implementing the slurry with lower corrosion inhibitor concentration. Although it may have slightly dishing issue after Cu polishing, it can be optimized by subsequent barrier polishing process.

The goal of this research is to improve bending issue and etch durability of amorphous carbon hard mask film (APF). The design of experiments (DoE) employed variable conditions of the spacing, RF power, precursors flow (C 3 H 6 or C 2 H 2 ) and temperature. High Young's modulus and high sp3/sp2 bonding ratio can increase the etching resistance, and strengthen the high aspect ratio patterning structures.

Thermal stability of titanium and cobalt silicides were enhanced by implementing nitrogen or argon implantation prior to silicide formation. Silicide formed on N2 or Ar implanted blanket wafers, P-type, or N-type poly-silicon had better thermal stability as compared with non-implant ones. Furthermore, Ar implanted approach demonstrated superior thermal stability characteristics even in a RTP test of 1000 °C/180 s. With the aid of N2 or Ar implantation, the grain growth of the silicide under high temperature was suppressed and thus it prohibited further diffusion and redistribution of the metal.

Dual gate oxide layers were implemented in 0.15 μm Mask ROM device. Two predominant approaches were carried out to achieve a combination of thin and thick gate oxides. One was the conventional, growth-etching-growth, process and another one was oxidation on wafers with pre-gate-oxide nitrogen implantation. The retardation rate of oxidation was dependent on the nitrogen implant dosage but independent on implant energy. For thin gate oxide, device performance by using nitrogen implantation prior to gate oxide demonstrated better thickness uniformity and breakdown voltage than that by using conventional approach. Furthermore, directly formed thick gate oxide achieved better thickness uniformity and breakdown voltage than that of the grow-etching-grow process.

A new polysilicon grain engineering technology for the improvement of over erase in 0.18-/spl mu/m floating-gate flash memory has been developed with the use of single-wafer polysilicon processing, which makes it practical to use hydrogen as a process variable. The addition of hydrogen in polysilicon deposition significantly alters the reaction kinetics and produces polysilicon thin film of smooth surface, fine and uniformly distributed grains. Such a micrograin polysilicon possesses show excellent high-temperature stability. The benefits of the micrograin polysilicon are to be demonstrated through its improvement in over erase of a 0.18-/spl mu/m floating-gate flash memory.

In this paper we studied capturing buried void defects in copper (Cu) wires using an electron beam inspection (EBI) system. These are defects of interest (DOI) to integrated circuit (IC) manufacturers because typical defect inspection techniques cannot capture them: optical defect inspection, EBI voltage contrast (VC) mode, and EBI physical detection mode. We used an engineering system to study a copper CMP wafer with a silicon nitride (SiN) cap layer. EBI backscattered electron (BSE) mode captured many dark defects. Defect review using both secondary electron (SE) and BSE modes found that some dark defects were voids exposed to the Cu surface, while others were unique to BSE mode. We did physical failure analysis (PFA) for some of the BSE mode unique DOI. The cross-sectional scanning electron microscope (SEM) images confirmed that the unique DOI were buried voids in copper wires. Monte Carlo simulation results confirmed there is enough contrast for BSE to differentiate between the normal Cu wire and Cu wire with buried void.

Airborne molecular contamination (AMC) becomes more serious in Fab as the device shrinks and wafer size increases, an economic way for preventing these contaminations is to use N2 purge charging process. The practical FOUP N2 purge engineering is addressed here, which includes the maintenance and management of FOUPs, N2 purge charging flow rate, the design of nozzle, selection of nuzzle material, and tool configuration.

The different inspection methodologies in e beam are put together to compare their inspection performance on irregularly periphery via plugs. The results demonstrate hot spot inspection mode has better alignment performance and higher sensitivity than leap and scan mode. Hot spot mode can inspect the tiny variation of voltage contrast (VC) with high sensitivities. One type of VC variation inspected by hot spot mode so call qausi-blind VC is addressed here that was not reported before.

Yield impacting systematic defects finding is no longer just relied on Design Rule Checking (DRC) provided by designer or Lithography Rule Checking (LRC) provided by post-optical proximity correction (OPC) results. An inspection flow is proposed in this paper, which is combining the inspection KLA tool and Hotspot Pattern Analyzer (HPA) database software to do the systematic defects filtering, sorting, grouping, and classification on the data base after hot scan inspection. 2nd time high sensitive inspection is done with new care area, which is reduced into one ten-thousandth of original inspection area. Following this inspection flow, we can identify the process window more accuracy.

Titanium nitride (TiN) not only was utilized in the wear-resistant coatings industry but it was also adopted in barrier processes for semiconductor manufacturing. Barrier processes include the titanium (Ti) and TiN processes, which are commonly used as diffusion barriers in via/contact applications. However, engineers frequently struggle at the via/contact module in the beginning of every technology node. As devices shrink, barrier processes become more challenging to overcome the both the physical fill-in and electrical performance requirements of advanced small via/contact plugs. The aim of this paper is to investigate various chemical vapor deposition (CVD) TiCl4-based barrier processes to serve the application of advanced small via/contact plugs and the metal gate processes. The results demonstrate that the plasma-enhanced chemical vapor deposition (PECVD) TiCl4-based Ti process needs to select a feasible process temperature to avoid Si surface corrosion by high-temperature chloride flow. Conventional high step coverage (HSC) CVD TiCl4-based TiN processes give much better impurity performance than metal organic chemical vapor deposition (MOCVD) TiN. However, the higher chloride content in HSC film may degrade the long-term reliability of the device. Furthermore, it is evidenced that a sequential flow deposition (SFD) CVD TiCl4-based process with multiple cycles can give much less chloride content, resulting in faster erase speeds and lower erase levels than that of conventional HSC TiN.

Various three-dimensional (3D) multilayer stacks NAND flash architectures are developed by several companies, the defect performance monitoring under such complicated architectures has become a new challenge in 3D NAND flash. The aim of this paper is to illustrate e beam inspection system can monitor the tiny, invisible defects and electrical defects that can not be recognized by optical systems.

Advanced bright field (BF) inspection tool bundles with many powerful features to improve its resolution and sensitivity. However, it usually takes much time for creating an effective monitoring recipe for suppressing the background signal. This paper demonstrates the benefit of BF dark mode inspection for suppressing the interferences of nuisance and pre-layer.

Advanced high performance dark field (DF) inspection is usually utilized at larger defects and the excursions in etch, chemical mechanical polish (CMP) or film deposition processes inspection at high production throughputs. Here demonstrates risky scratch defects right after post poly-silicon CMP captured by DF inspection technique.

The effects on the mini-environment of FOUP (Front Opening Unified Pod) by N 2 purge are evaluated with various processes. From the experimental results, it is effective to suppress the formation of condense defect, corrosion defect and extend the queue time at critical process steps.

Advanced bright field (BF) inspector have many functions to increase the defect signal, and suppress the background noise. However, it will take much time to fine tune an optimized BF inspection recipe. The aim of this paper is to propose a faster way to select the optimized optics.

This investigation employs an optimized method to alleviate defects occurring at BF 2 + implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various approaches which includes changing the stress of post cap layer, lowering down the BF 2 + implant doping concentration, and optimizing the ramp-up speed of post-annealing are all able to alleviate the generation of white spot defects. The optimized process with an additional RTP (rapid thermal annealing) right after BF 2 + implantation delivers 7% yield improvement.

For the first time a unipolar resistance memory with good performance and reliability is demonstrated. A short (20-50 ns) positive pulse switches the WOx film from low resistance state (LRS) to high resistance state (HRS), while a longer (200-500 ns) positive pulse switches the film from HRS to LRS. Negative pulses, on the other hand, do not produce reversible resistivity changes. Despite the low energy switching, both LRS and HRS are very stable, capable of withstanding 2,500 hours of baking at up to 150 degC- Furthermore, the WOx R-RAM can withstand > 1,000 cycles of LRS/HRS switching, and the device is also highly immune to read disturb. This unipolar device is promising for future 3D high-density NVM storage.

Plasma damaged 0.18 /spl mu/m flash memory device has been resolved by integrating advanced process control with fault detection and classification (APC FDC) system in ILD HDP PSG process. PSG plasma damage to device was detected by real-time monitoring APC control system with multivariate statistically calculation to detect out-of-control conditions within five minutes. The unhealthy recipe contents and the hardware healthy status are detected by integrating APC FDC system. After we analyzing the fault detection and classification function, APC system successfully predicts the same results as wafer acceptance test and wafer sort yield. Recipe and hardware are modified to eliminate the plasma damage according the analysis results.