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This paper delves into an in-depth exploration of speaker recognition methodologies, with a primary focus on three pivotal approaches: feature-level fusion, dimension reduction employing principal component analysis (PCA) and independent component analysis (ICA), and feature optimization through a genetic algorithm (GA) and the marine predator algorithm (MPA). This study conducts comprehensive experiments across diverse speech datasets characterized by varying noise levels and speaker counts. Impressively, the research yields exceptional results across different datasets and classifiers. For instance, on the TIMIT babble noise dataset (120 speakers), feature fusion achieves a remarkable speaker identification accuracy of 92.7%, while various feature optimization techniques combined with K nearest neighbor (KNN) and linear discriminant (LD) classifiers result in a speaker verification equal error rate (SV EER) of 0.7%. Notably, this study achieves a speaker identification accuracy of 93.5% and SV EER of 0.13% on the TIMIT babble noise dataset (630 speakers) using a KNN classifier with feature optimization. On the TIMIT white noise dataset (120 and 630 speakers), speaker identification accuracies of 93.3% and 83.5%, along with SV EER values of 0.58% and 0.13%, respectively, were attained utilizing PCA dimension reduction and feature optimization techniques (PCA-MPA) with KNN classifiers. Furthermore, on the voxceleb1 dataset, PCA-MPA feature optimization with KNN classifiers achieves a speaker identification accuracy of 95.2% and an SV EER of 1.8%. These findings underscore the significant enhancement in computational speed and speaker recognition performance facilitated by feature optimization strategies.

This article introduces a programmable Artificial Intelligence Visual System on Chip (AIV-SoC), optimized for YOLOv8 end-to-end execution. It operates on input image resolution of $352\times 352$ to perform object detection, instance segmentation, and pose detection, achieving notable Frames per Second (FPS) of 67.1, 55.2, and 64.9, respectively. The AIV-SoC is founded on the RISC-V architecture and meticulously crafted utilizing the LLVM-C2RTL toolkit. Neural network layer scheme optimization, piecewise linear function (PLF) approximation, multi-cycle path, 8-bit fix-point data per-group quantization and 4-pattern transposed convolution are introduced to enhance its versatility and power efficiency. Notably, the implemented model exhibits superior power efficiency in comparison to other GPU and FPGA platforms. This characteristic envisions practical applications across industries. The presented AIV-SoC platform, with its efficiency, opens up possibilities for deployment in resource-constrained environments such as healthcare, agriculture, and surveillance. This potential redefines the landscape of object detection, instance segmentation, and pose detection in real-world scenarios, providing insight into a future where these technologies play a pivotal role in reshaping how we interact with machines and interpret visual information.