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In this paper, we generalize the lightweight-slope piecewise-line range-addressable lookup table for efficient approximate computing in any activation/quantization function, and propose an error-correcting algorithm and circuitry using the AN codes for enhancing reliability. A BLER/SNR simulation proves the SEC/DEC capability of the firstly-presented AN-coded neuron. Comparisons with similar state-of-the-art works show that the proposed technique is the most efficient and error-correctable lookup table for any function in a medium resolution within 8-12 bits.

AI techniques have been widely applied in consumer electronics, especially automotive advanced driver assistant systems. The reliability of the AI processors in the harsh environment is facing a critical challenge. In this paper we explore and exploit high correlation between single-aging-factor (SAF) enhanced oscillating rings (SAFERs) for online data annotation in early stage and SAF shadow trees (SAFESTs) for training and on-line aging monitoring later. Compared with previous work, 88% of accuracy for high correlation supervised classification will be more reliable than 99% of meaningless clustering.

Acceleration and reliability are two critical issues of artificial intelligent circuits and systems. In this paper we propose a novel structure of deep neural network in testing stage that converts the trained weights to optimized ternary-coded binary. Within each shallow layer a constant-shift sub-layer with almostfree cost is inserted to transfer all multipliers to a carry save adder/subtractor. Then the activation functions are simplified to piecewise lines with nice slopes for calculation by an adder only. Since input-side layers tend to have self-healing ability, only output-side layers are equipped by AN codes that can be encoded and decoded almost without extra cost in our structure. From experiments and evaluations, our structure can have a higher resolution with error-correcting capability and a performance similar to the BNN.

Sigmoidal activation functions play a key role in AI accelerators. They have been usually implemented by hyperbolic sine and cosine functions with a division since the CORDIC algorithm was proposed in 1956 and unified in 1971. From all literature it seems that people have never tried the simple algorithm proposed in this paper, in which only a half-domain exponential function is applied prior to a Booth division. More than one half of iterations and area can be reduced. From experimental results, both the area overhead and the power consumption can be reduced to only 1/3. The acceleration in backpropagation and learning rate can then be highly improved.

Neuromorphic RRAM has become the most promising candidate for AI applications. But it suffers three issues including degradation, defects and errors. To overcome the three issues we proposed a precompensation technique for compensating resistive degradation. A linear-system-based BIST architecture is developed with proposed diagonal sliding march test can effectively and efficiently screen out the uncompensated degradation and permanent defects. Analog Berger codes is proposed for detecting transient errors for variation learning and self-checking for asymmetric errors. From evaluations, the precompensation takes only 5/B time for batch operations of B cycles. Proposed BIST approach and method can reduced 2LN march tests to 6N for L-level RRAMs. The self-healing ability is verified by analog-Berger-code error detection. From experiments using a typical neural network for MNIST handwritten digit dataset the network can be healed with only 2% of accuracy and about 35% of training steps.

As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.

Contiguity along Gray codes and neighborhood among cluster faults are naturally connected by a novel hypercube-based address remapping unit. A novel memory repair architecture based on redundant hypercube is proposed, which mainly consists of a modified ternary CAM with an address concentrator. A modified ESPRESSO tool is developed for redundancy analysis on clustered-fault repairing optimization. Based on the redundancy analysis for a two-dimensional Gray-code-ordered memory array, every clustered fault with a width of no more than w and a length of no more than l can be repaired by a single hypercube-based spare row with a degree of \( \left( {\lceil \log 2(w - 1)\rceil +1} \right)\;\left( {\lceil \log 2(l - 1)\rceil + 1} \right) \). Finally 100% of repair rate can be obtained using only a few equivalent rows.

A novel memory repair architecture based on redundant hypercube is proposed, which mainly consists of a modified ternary CAM with an address bubble-shifter. Generally for an acceptable repair rate about 3% of spare sub cubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work.

Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.

Digital synchronous mirror delaylines can lock in only two cycles and make burst and sleep modes feasible for high-speed and low-power applications. Conventional digital synchronous mirror delay usually spends at least one delay line with a length comparable to the resolution. The area overhead becomes an issue in multiple-module circuits. The objective of this paper is thus to reduce the area overhead by folding the delayline. Simple corollaries from the congruence theorem are derived for function proves. Experimental results show that the proposed design can save more than 75% of area overhead for fixed skew compensation of hundreds of stages under acceptable phase errors.

Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average

Power-gating is an effective approach for reducing both dynamic and static power dissipation in power management and test scheduling. This paper formulates the power-gating spike problem, derives a reduced power dissipation model as heuristics, proposes a vector control technique for post-gating circuits, and develops a sleep-transistor allocation scheme for power-on/off current spikes reduction of pre-gating systems. From experimental results, a justified controlling vector can reduce the on/off peak power up to 55%. For a pre-gating system, more than 83% of the power-gating spike can be reduced. From our preliminary simulations using HSPICE so far, this heuristics has been proved to reduce the supply-gating current spike

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.

This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.