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Switching dynamics of perpendicular magnetic tunnel junction (MTJ) driven by spin–orbit torque (SOT) are investigated by the Landau–Lifshitz–Gilbert (LLG)-based physical model considering the temperature dependence. The field-assisted switching method is proposed to develop the reliable sub-ns writing of SOT-magnetoresistive random-access memory (SOT-MRAM) by removing the plateau time. The conventional method of SOT-MTJ requires the large write current, leading to the area increase of access transistors and the penalty of memory density. The write current and the switching time of SOT-MTJ can be efficiently reduced at the same time by our field-assisted method using the enhanced magnetic field. The magnetic field can be provided by the Co magnetic hard mask above the MTJ. Considering an SOT-MRAM array, the surrounded Co metals have the insignificant influence of stray magnetic field on an MTJ at the center. With the write time of 0.2 ns, the 60% reduction of write current is achieved by our field-assisted method compared to the conventional method. The required write current for the SOT switching decreases with the increasing temperature due to the lowering of thermal stability factor. The write Shmoo plots are further analyzed to calculate the write current margin at the various working temperature. The write time of 0.2 ns exhibits the narrow margin of write current ( $2.6~\mu \text{A}$ ) in the temperature range from 25 °C to 85 °C, while the write time of 0.8 ns has the wide write margin of $102~\mu \text{A}$ . The switching behavior and the write margin are also sensitive to the magnetic field.

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The tensily strained high Ge content (85%) GeSi multi-channels stacked on the Si channel with channel size optimization have good subthreshold behaviors (SS, DIBL, and $\mathrm{I}_{\mathrm{off}}$ ), and meanwhile maintain high $\mathrm{I}_{\mathrm{on}}$ . By narrowing GeSi channel, the bandgap of the GeSi can be increased by quantum confinement and the short channel effect can be suppressed. This also causes the more positive $\mathrm{v}_{\mathrm{t}}$ for GeSi than Si. As a result, $\mathrm{SS}=76\mathrm{mV}/\mathrm{dec}, \mathrm{DIBL}=36\ \mathrm{mV}/\mathrm{V}$ can be achieved due to the benefit of superior subthreshold behaviors of the Si channel underneath. The $\mathrm{I}_{\mathrm{on}}/\mathrm{I}_{\mathrm{off}}$ is improves to be 1.2E7. The high $\mathrm{I}_{\mathrm{on}}=44\mu \mathrm{A}$ perstack at $\mathrm{Vov}= \mathrm{V}_{\mathrm{DS}}=1\mathrm{V}$ , is contributed from both the GeSi and Si channels, and it is further enhanced to $46\ \mu \mathrm{A}$ by the external strain. The relatively low flicker noise indicates that the novel structure can mitigate the reliability issue of GeSi channels by the highly reliable Si channel underneath.

High material quality of compressively strained GeSn quantum wells sandwiched by Ge barriers on 200mm SOI wafers by CVD are confirmed by reciprocal space mapping (RSM), X-ray diffraction (XRD), and photoluminescence (PL). Due to the growth of relaxed Ge buffer on SOI, the misfit dislocations are confined near the Ge buffer/SOI interface, yielding low defect densities in the stacked GeSn channels. The low selectivity of Cl 2 /HBr between GeSn and Ge, makes it impossible to perform the channel release for stacked devices by etching away the Ge barriers. The channel release by optimum H 2 O 2 etching for stacked two GeSn nanowires with [Sn] = 6%, hole concentration = 1.3E19cm−3, and channel length (L CH ) = 150nm yields I on per channel width = 1400μA/μm for junctionless (JL) devices. Further improvement of Ion to reach record value of I on = 1850 p.A/p.m is achieved by increasing [Sn] to 10%, hole concentration to 6.7E19cm−3 and reducing the L CH to 60nm. Additional 6.3% enhancement of I on is obtained by additional uniaxial compressive strain using wafer bending. The best SS values of 84mV/dec and 88mV/dec are obtained for single-wire and stacked two-wire channels, respectively. JL has lower low frequency (LF) noise than inversion mode (IM) due to its bulk conduction nature. The mobility of JL and IM is dominated by impurity scattering and phonon scattering, respectively, according to the temperature dependence.