32 results on '"Trivedi, V.P."'
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2. Bulk Inversion in FinFETs and Implied Insights on Effective Gate Width
3. Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs
4. UFDC, and nanoscale FinFET-CMOS design and performance projections
5. A process/physics-based compact model for nonclassical CMOS device and circuit design
6. A 77GHz CMOS VCO with 11.3GHz tuning range, 6dBm output power, and competitive phase noise in 65nm bulk CMOS.
7. A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOS.
8. On-chip artificial transmission lines, enabling compact Si-based mmWave ICs.
9. Suppression of corner effects in triple-gate MOSFETs
10. Scaling fully depleted SOI CMOS
11. Hyperabrupt-junction varactor for mmWave SiGe:C BiCMOS, enabling 77GHz VCO/TX with 13-15GHz tuning range.
12. A tunable flipflop-based frequency divider up to 113 GHz and a fully differential 77GHz push-push VCO in SiGe BiCMOS technology.
13. An evaluation of toxicity of Taxus baccata Linn. (Talispatra) in experimental animals
14. Physics-based compact modeling for nonclassical CMOS.
15. A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices.
16. Pragmatic design of nanoscale multi-gate CMOS.
17. The effect of N2 plasma damage on AlGaAs/InGaAs/GaAs high electron mobility transistors. I. DC characteristics
18. Toxicity of a Novel Herbomineral Preparation Las01 on Human Cancer Cell Lines and Its Safety Profile in Humans and Animals.
19. Bulk inversion in FinFETs and the implied insignificance of the effective gate width.
20. Source/drain-doping engineering for optimal nanoscale FinFET design.
21. Non-classical CMOS device design.
22. Physics-based compact modeling for nonclassical CMOS
23. Bulk inversion in FinFETs and the implied insignificance of the effective gate width
24. Pragmatic design of nanoscaleimulti-gate CMOS
25. Physical insights on design and modeling of nanoscale FinFETs
26. A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices
27. Source/drain-doping engineering for optimal nanoscale FinFET design
28. A Novel Two-Transistor Floating-Body Memory Cell.
29. High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS.
30. Insights on Carrier Mobilities and Transport in Contemporary DG FinFETs.
31. Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS.
32. Extremely scaled fully depleted SOI CMOS.
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