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As discussed in Section 1.1.2, the design of a DSP system basically involves two fundamental tasks, namely, the analysis of the input signal and the design of a processing system to give the desired output. There are several different mathematical tools for carrying out these two tasks. A time-domain approach was presented in Chapter 1, where a sampled input signal was represented by a weighted unit-impulse train and a DSP system was described by either a general difference equation or a unit-impulse response. A frequency-domain approach based on the z-transform was presented in Chapter 2, where an infinite data sequence was converted to an algebraic equation and a DSP system was described compactly by a transfer function; the former enables the frequency spectrum of a signal to be estimated and the latter enables the stability and the frequency response of a DSP system to be assessed.

The numerous worked examples and the case studies contained in this book clearly demonstrate that digital signal processing operations are governed by discrete-time representations of algorithmic processes. For example, we have seen that the characteristic performance of a digital filter is determined by its linear difference equation. The practical implementation of real-time digital signal processing operations is generally achieved using one of two practical options, namely (a) using dedicated hardware, such as an application specific integrated-circuit (ASIC) or a bit-slice processor, or (b) using a programmable integrated-circuit (microprocessor or digital signal processor chip). If the processing operations are not required as real-time implementations, then it is often appropriate to perform the DSP computations using a general-purpose personal computer (PC). For example, a number of proprietary software packages have been produced to enable model definitions and simulation of DSP systems.

Digital Signal Processing (DSP) is concerned with the use of programmable digital hardware and software (digital systems) to perform mathematical operations on a sequence of discrete numbers (a digital signal). Such processing is needed to facilitate the extraction of information embedded in the signal.

With the emergence of Broadband ISDN and the adoption of ATM as its transport mechanism there is a growing interest in slotted ring networks both for high speed packet switching and for multimedia LAN applications. This paper describes a slotted ring testbed which uses a modified Orwell protocol for media access, and which has enabled a study of the modified Orwell protocol under symmetrical and asymmetrical traffic flow distributions. The architecture of the slotted ring testbed is outlined, and analytical models for the protocol are presented for different traffic flow distributions. The analytical results are compared to experimental results obtained from the testbed. The suitability of the reset rate as an indicator of available bandwidth in an access control mechanism is considered, and it is shown that for constant traffic flow and traffic statistics the reset rate works well as an indicator of potential network congestion. Under changing traffic distributions and traffic arrival statistics, additional indicators of congestion are required. On-going work into access control for the test-bed in a integrated services environment is outlined.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The concepts of microprocessor-based signal filters are presented via a case study of a simple low-pass filter designed using the bilinear z-transform method. The paper provides a general introduction to signal filtering using microprocessor-based forms of implementation, and discusses several alternative system configurations based on commercially available microprocessors or special purpose integrated circuits.

The concepts of single-chip digital signal processing are presented via a student-oriented tutorial/laboratory case study. This involves the design of a highpass digital filter using the first-difference design method and its implementation using the NEC μPD7720 Signal Processor.

The concepts of digital filtering using the NEC μPD7720 single-chip digital signal processor are presented. The architecture and instruction formats of the device are summarised. The design philosophy and practical hardware and software considerations of using the 7720 as a peripheral to a host 8085 microprocessor system are discussed.

The architecture, implementation and image processing facilities of the LS10 low-cost microprocessor-based image processing system are described. The paper presents a summary of the system's attributes, and emphasis is given to their use in practical image processing applications. Results for processed Landsat satellite images are presented and described to illustrate the performance achievable from the system. To perform complex computations rapidly, fast Fourier transforms for example, a transputer-based processor has been developed. The paper shows how this sytem can be interfaced to the image processor.

Recursive digital filters are commonly referred to as infinite impulse response (IIR) filters. The term recursive intrinsically means that the output of the digital filter, y(n)T, is computed using the present input, x(n)T, and previous inputs and outputs, namely, x(n − 1)T, x(n − 2)T,…, y(n − 1)T, y(n − 2)T,…, respectively.

A microprocessor-based system (microcomputer) normally consists of a number of interconnected integrated circuits. This chapter presents a block diagram of a simple system comprising a microprocessor unit (MPU), memory for storing instructions and data, and some input/output (I/O) capability, and it discusses the basic concept of a microprocessor-based system and the method whereby an instruction is fetched and executed. It also discusses hardware system elements and their relevant signals for system operation. The chapter shows the way by which the elements may be put together into a specified, practical dedicated system and describes the associated memory-mapping philosophy. The MPU operation is categorized into two cycles of operation. Serial asynchronous data communication between peripheral equipment and the 6800/6802 MPU can be achieved using the 6850 asynchronous communications interface adapter (ACIA). The interface includes select, enable, read/write, and interrupt logic to allow bidirectional data transfer. The parallel data of the MPU system is serially received and transmitted by the ACIA with necessary formatting and error checking. The functional configuration of the device is programmed using the data bus during the initialization of the system.

This chapter presents details of 12 investigations, which may be undertaken using the MEK6802D5E evaluation system. Investigations 1 to 4 described in the chapter were concerned with operating the basic evaluation system. Investigations 5 and 6 were concerned with interfacing a one-byte, memory-mapped display to the basic evaluation system. In Investigations 7 and 8, use was made of the user peripheral interface adapter (PIA) on board the MEK6802D5E to input and output data. This work was extended in investigation 9 by interfacing the evaluation system to an 8 bit digital-to-analogue converter to generate saw-tooth and triangular waveforms. A signal processing case study based on a simple digital filter forms the basis of investigation 10. Investigation 11 is concerned with connecting the evaluation system to a teletype, via an ssynchronous communications interface adapter (ACIA) and 20 mA current-loop interface to provide the capability of printing a predetermined message when the associated designated user-defined function is selected.

Having selected or derived the desired digital filter pulse transfer function, G(Z), (see chapter 2 and chapter 3) and, furthermore, having determined the appropriate processor word length (see chapter 4), then the next step is to undertake the implementation of the filter’s linear difference equation corresponding to G(Z). This linear difference equation is used to compute the filter’s output y(n)T values, which will be a filtered version of the filter’s input x(n)T values (see figure 1.1).

This chapter presents basic principles of flowcharting, modes of addressing, and instructions. It discusses machine-code programming using worked examples. The instruction is used to operate the hardware to perform the desired task; therefore, when instructions are put together in the correct order, they form a program that establishes the operation of the microprocessor system. The first consideration in preparing a program is to establish the logical sequence of steps to be performed by the microprocessor system to accomplish the desired operations. The initial preparation generally involves drawing a flowchart that illustrates diagrammatically the steps involved. A flowchart is made up of graphical symbols that are connected together by straight lines. Arrow-heads are drawn on the connecting lines to indicate the direction of flow in the program. The 6800/6802 microprocessor has six addressing modes available to the programmer: (1) inherent (accumulator or implied) addressing, (2) immediate addressing, (3) direct addressing, (4) extended addressing, (5) indexed addressing, and (6) relative addressing.

Non-recursive digital filters have a weighting sequence (impulse response), g(i)T, which is finite in length, and consequently this type of filter is commonly referred to as a finite impulse response (FIR) filter. The term non-recursive intrinsically means that the output of the filter, y(n)T, is computed using the present input, x(n)T, and previous inputs, x(n − 1)T, x(n − 2)T,…, and furthermore the filter has no inherent feedback, which means that previous output values, y(n − 1)T, y(n − 2)T,…, are not used in the computation of y(n)T. Figure 3.1 shows a typical example of a non-recursive filter; the arrangement shown is a digital transversal filter.1

Digital filters have been successfully implemented using digital minicomputers1,2, microprocessors3,4 and dedicated hardware.5 The implementation of the filter involves, to some degree, using hardware having finite word lengths (16 bits, 12 bits or 8 bits are typical). These finite word lengths represent sampled-data input and output signals, filter coefficients and results of arithmetic computations; consequently inherent errors exist in the representation of these parameters, and they normally take the form of (1) quantisation errors which arise as a result of arithmetic computations (round off and truncation errors); (2) quantisation errors due to representing the input signal by a set of discrete values; (3) quantisation errors due to representing the filter coefficients by a finite number of bits; (4) limit cycle oscillations; and (5) overflow oscillations. The design of the filter can be undertaken without detailed consideration of the effects of finite word lengths (see chapter 2 and chapter 3). However, in contrast, in the practical implementation of the filter the errors listed above in (1) to (5) inclusive, must be considered, and they must be eliminated or kept as small as possible.

This chapter describes the MEK6802D5E evaluation system, and it presents reference information to undertake the hands-on experience of 6800/6802 program execution and microprocessor system operation and development. The D5BUG monitor program requires 128 bytes of static RAM for the operating system, that is, memory locations E400 to E47F. This provides memory for storage of flag and data information and stack area for the monitor. However, 24 bytes are provided as a user-stack area. The chapter presents a summary of some useful D5BUG operating system RAM locations. The content of a memory location can be displayed or changed using the memory display /change editor. This is achieved by a keypad entry of the specified memory location address (leading zeros unnecessary), followed by pressing the M key. It results in the address and current data content being displayed. The memory address display can be incremented by one by a single pressing of the GO key, or it may be decremented by one by a single pressing of the M key. In all cases, the current memory content will be displayed for the accessed memory location. Therefore, a program may be entered and modified as required.

Arithmetic operations in microprocessor systems are undertaken using binary numbers' and, therefore, to study microprocessor systems, it is necessary to understand several aspects of digital systems. Microprocessor systems are implemented using hardware elements having two stable states. For example, the binary states may represent voltage levels, current levels or magnetic field directions, and in all cases, one of the stable states is denoted by 1 and the other by 0. The weight of each binary digit (bit) is governed by its position and by the radix. For example, the binary number 1010.01 2 may be written as (1 × 2 3 ) + (0 × 2 2 ) + (1 × 2 1 ) + (0 × 2°) + (0 × 2 -1 ) + (1 × 2 -2 ) = 10.25 10 . There are three important considerations in representing a number: (1) the radix or base, (2) the positional significance of characters, and (3) the need to represent zero. Hexadecimal numbers are a convenient and very useful shorthand representation of their equivalent binary form. This system has a radix of sixteen and uses alphanumeric characters. It uses the numeric characters 0 to 9 and the alphabetic characters A to F. This chapter describes the rules of binary arithmetic, conversion of a decimal number to its radix r equivalent, uses of binary-coded-decimal numbers, important features of logic elements, flip-flops, registers, and counters.

When a microprocessor is used to control a system, it must be capable of accepting input information, responding, and outputting appropriate signals to implement the required control action. The input/output (I/O) signals may have to be subjected to signal conditioning so that their forms and levels are compatible with the input/output interface elements. The chapter highlights this point by considering two contrasting practical examples. A common technique employed in microprocessor interfacing is to establish the I/O interface as a memory-mapped device. The peripheral interface adapter (PIA) has two 8 bit bidirectional data buses (PA0 to PA7, and PB0 to PB7) for interfacing with peripheral equipment and four control lines CA1, CA2, CB1, and CB2. Each bidirectional data line must be initialized to act as either an input or an output. This is achieved by setting a 0 in the corresponding bit in the data direction register (DDR) if the line is to be an input or a 1 if the line is to be an output.