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Traffic jams have been occurring recently on most city street networks. These jams can be avoided by predicting the traffic flow patterns in advance using computers. The reduction of computer time is very important, especially in the case of real-time prediction of traffic flows. This paper develops a special-purpose simulator for calculating road traffic flows. The simulator consists of several transputers and a random number generator. Large and complex street networks are partitioned, and each partition is assigned to a transputer for parallel calculations. The stochastic nature of the traffic is taken into account by using random numbers generated by a random number generator. Some traffic flow patterns are calculated with this simulator. The developed simulator can simulate large and complex street networks using a small amount of computer time. Index Terms - Random number, traffic flow, transputer.

The Kalman tracking algorithm estimates position, velocity, and acceleration of a target from noisy measurement. A parallel Kalman algorithm is derived using the row-column partitioning with the modified state vector representation for multiprocessor realization. Mapping the tasks onto the multiprocessor system to minimize the time needed to complete all the tasks is an NP hard problem, and it arises when the task dependency structure of a parallel algorithm differs from the processor interconnection topology or when the number of processes generated by the algorithm exceeds the number of processors available. The efficient mapping of 3D-3S parallel Kalman tracking algorithm onto the network of 10 transputers, which are connected in tree structure that achieves a speedup of 6 is presented here.

An efficient packet routing network to support interprocessor communications between a large Transputer population is proposed. The network uses a simple multiple bus interconnection. Among the significant features of such a two-dimensional network are low communication latency, scalable bandwidth and deadlock freedom. The scalable property of such a configuration makes it suitable for further exploring efficient communication networks in highly parallel systems.

This paper analyzes parallel implementation of the backpropagation training algorithm on a heterogeneous transputer network (i.e., transputers of different speed and memory) connected in a pipelined ring topology. Training-set parallelism is employed as the parallelizing paradigm for the backpropagation algorithm. It is shown through analysis that finding the optimal allocation of the training patterns amongst the processors to minimize the time for a training epoch is a mixed integer programming problem. Using mixed integer programming optimal pattern allocations for heterogeneous processor networks having a mixture of T805-20 (20 MHz) and T805-25 (25 MHz) transputers are theoretically found out for two benchmark problems. The time for an epoch corresponding to the optimal pattern allocations is then obtained experimentally for the benchmark problems from the T805-20, T805-25 heterogeneous networks. A Monte Carlo simulation study is carried out to statistically verify the optimality of the epoch time obtained from the mixed integer programming based allocations. In this study pattern allocations are randomly generated and the corresponding time for an epoch is experimentally obtained from the heterogeneous network. The mean and standard deviation for the epoch times from the random allocations are then compared with the optimal epoch time. The results show the optimal epoch time to be always lower than the mean epoch times by more than three standard deviations (3[Sigma]) for all the sample sizes used in the study thus giving validity to the theoretical analysis.

The paper reports and discusses results from a Danish mechatronic research program focusing on intelligent actuators for intelligent motion control. A mechatronic test facility with a transputer controlled hydraulic robot suitable for real-time experimentation and evaluation of control laws and algorithms is described. Concepts of intelligent motion control and intelligent hydraulic actuators are proposed. Promising experimental path-tracking results obtained from model-based adaptive control algorithms are presented and discussed. The experiments confirm that transputers have significant advantages in intelligent control of actuators and robots for high-speed and high-precision tasks. Further, research on learning controllers and hybrid controller architecture, including real-time switching between control algorithms, benefits from applying transputer technology.

In this paper a new simulator for cellular neural networks (CNN) called PSIMCNN is presented. It has been studied for a parallel general-purpose computing architecture based on transputers. The Gauss-Jacobi waveform relaxation (WR) algorithm has been adopted. It has been analytically proved that the WR algorithm is convergent for the most common CNN models. Implementation issues have been described and some experimental results comprising classical CNN and Chua circuits CNN simulations have been presented. Parallelism and performances have been investigated. Moreover, a comparison with the CNN-HAC simulator is reported. Key words: Cellular neural networks, simulators, non-linear circuits, transputer, parallel processing.

We have developed a TDC+Transputer-based acquisition system to study the X-ray imaging capabilities of a silicon [micro]strip detector with 100 and 200 [[micro]meter] read-out pitch. This system allows real-time image acquisition and display. We present images obtained with an X-ray mammography tube using sub-millimeter high contrast test objects on a 16*16 channels prototype.

In this paper a pipelined ring algorithm is presented for efficient computation of one and two dimensional Fast Fourier Transform (FFT) on a message passing multiprocessor. The algorithm has been implemented on a transputer based system and experiments reveal that the algorithm is very efficient. A model for analysing the performance of the algorithm is developed from its computation-communication characteristics. Expressions for execution time, speedup and efficiency are obtained and these expressions are validated with experimental results obtained on a four transputer system. The analytical model is then used to estimate the performance of the algorithm for different number of processors, and for different sizes of the input data.

A performance analysis is presented that focuses on the achievable speedup of a neural network implementation and on the optimal size of a processor network (transputers or multicomputers that communicate in a comparable manner). For fully and randomly connected neural networks the topology of the processor network can only have a small, constant effect on the iteration time. With randomly connected neural networks, even severely limiting node fan-in has only a negligible effect on decreasing the communication overhead. The class of modular neural networks is studied as a separate case which is shown to have better implementation characteristics. On the basis of implementation constraints, it is argued that randomly connected neural networks cannot be realistic models of the brain.

A flexible LINDA 2 language system is implemented on a distributed memory parallel system built using Transputers. This is innovative for its high modularity, permittance of recursive functions to use eval() operator and easy adaptation to applications such as bigger machines. Its modularity does not result in inefficiency, although only LINDA operator fundamental types are supported. Tuple matching semantics have to be redefined for derived types to be applicable. The system runs on a four node machine and can be extended to LINDA 3. A common numeric integration problem was applied.

Real-time simulation of large power systems is a requirement for tasks as varied as operator training and the testing of new devices such as relays. Until recently, the network portion of the simulator (the Transient Network Analyzer, or TNA) was of necessity implemented with analog hardware. This paper reports on the development of a completely digital multiprocessor TNA with the following characteristics: * One processor is assigned for each bus in the network being simulated. The topology of the TNA is identical to that of the network. * There is no limit to the size of the network which can be simulated. The simulator is extensible. * The integration step size is under 100 microsecs making possible the simulation of electromagnetic transient phenomena. * The processor used is the transputer, a novel microprocessor designed especially to handle interprocessor communication. * Use of the transputer keeps the cost per node of the simulator to a minimum.

Reduction operations as applied to distributed memory machines with reconfigurable interconnection networks are analyzed. A proposed method for implementing these operations assumes that the interconnection network is tree-based and every node transmits reduction results to the parent node. The best interconnection topology is derived as an indicator of processor quantity and machine-dependent parameters. Experimental results conform well with theoretical predictions.