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Besides silicon semiconductor technologies more and more plastic integrated circuits attracts the attention of the scientific world. Polymer technology is not expected to replace silicon technology but to fill a gap in the low cost and short lifetime market of the semiconductor industry. Reel-to-reel manufacturing, as used in the printing press, with nearly endless substrates of organic foil revolutionizes the time saving and cost efficient processing of organic semiconductor devices at room-temperature. The economical efficiency of these processes can't be reached with silicon technologies. Therefore polymer electronic integrated circuits may be used for controlling products in supermarkets or within any kind of tickets or clothes. In this paper the capacitance voltage behaviour of an organic metal-insulator-semiconductor thin film transistor (oMISTFT), the basis of any polymer-electronic circuit, shall be investigated. Moreover the frequency dependence of the organic insulator polystyrene (PS) and the organic semiconductor polyarylamine (PAA) shall be analyzed. Index Terms--Organic metal-insulator-semiconductor thin-film-transistor (oMISTFT), polystyrene (PS), polyarylamine (PAA), reel-to-reel manufacturing, C-V measurements, insulator capacitance, space-charge capacitance, frequency, permittivity, life-time, mobility.

It is shown that combined application of the SiGe source and the delta-doped p[superscript +] region on the source side in the body of a partially depleted (PD) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) can greatly improve breakdown voltage, and high immunity to single transistor latch can be achieved.

Research is presented describing the study of superconducting electronics properties which resemble transistor elements and support low temperature applications.

A transistor circuit consisting of linear positive resistors, q exponential diodes, and p Ebers-Moll modeled bipolar transistors has at most (d +1)(super d)(super d 1)/super 2) isolated dc operating points where d = qx2p. If, instead of bipolar transistors, the circuit employs Shickman-Hodges modeled field-effect transistors, then it can have at most 2(super p)3(super 2p)(4p+q+1)(super q)2(super q)(super q-1)/super 2) isolated dc operating points. Bounds are also obtained for the number of dc operating points in circuits using other transistor models. Index Terms: DC operating points, transistor circuits.

A detailed analysis of the transistor chain operation of CMOS gates is introduced. The chain is modeled by a transistor pair, according to the operating conditions of the structure. The system of differential equations for the derived chain model is solved and analytical expressions which accurately describe the temporal evolution of the output voltage are extracted. For the first time, a fully mathematical analysis without simplified step inputs and linear approximations of the output waveform, and without resistors replacing transistors, is presented. The width of the equivalent transistor that replaces all nonsaturated devices is efficiently calculated, eliminating previous inconsistencies in chain currents. A mapping algorithm for all possible input patters to a scheme that can be handled analytically is also derived. The final results for the calculated response and the propagation delay of this structure are in excellent agreement with SPICE simulations. Index terms: Modeling, simulation, timing analysis, transistor chain.

A study was conducted to investigate the possibility of compact modeling in single-electron circuit. It was shown that each Coulomb island in single-electron circuits can be treated separately provided that the interconnections between single-electron transistors are sufficiently big and a quantitative criterion for this condition is known. In these situations, it was also shown that SPICE macromodeling of single-electron transistors can be employed for efficient circuit simulation.

Research was conducted to examine the Bloch transistor with Al/AlO(sub x)/Al small tunnel junctions which is furnished with a Au/Cr on-chip shunt. To control the induced charge of the small intermediate electrode of the transistor, a capacitively coupled gate was supplied. No hysteresis was observed with measured current-voltage curves. Results show that the current-voltage curves were modulated by the gate with a period of e and a maximum swing of around 2 microV.

SPICE macro models for magnetic MOSFET (MAGFET) devices in the saturation region are presented. By using the proposed models, the performance of several readout circuits using MAGFET devices could be predictable. In this paper, the magnetic field-to-voltage converter, the magnetically controlled operational-transconductance amplifier, and the magnetically controlled filter and magnetic-operational amplifier using MAGFET devices have been designed, simulated, and tested. The proposed readout circuits using two different CMOS processes have been fabricated. Both simulation and measurement results verify the correctness and flexibility of the proposed SPICE macro models. Index Terms - Magnetic, MOSFET, circuit, sensor.

Research has established a novel way of simulating AlGaAs/GaAs heterojunction bipolar transistor (HBT) circuits in a burn-in test using the SPICE model. The performance of HBT circuits following electrical and thermal stress was assessed. Experimental evidence shows that the model produces agreeable results with two-dimensional device simulation.

We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 [Mu] CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 [Mu] CMOS technology has been experimentally verified. Index Terms - Adiabatic computing, energy recovery, low power logic.

The fabrication of a gate-controlled lateral PNP transistor having four electrodes, namely collector, base, emitter and gate, uses BiCMOS technology. The presence of internal hybrid device features of a surface PMOS and a bulk lateral PNP in parallel impart unique large signal DC characteristics to this transistor. This device helps in building of functional analog circuits such as a variable-gain amplifier and a mixer circuit. The device in conjunction with other digital and analog signal processing circuits provides applications in portable wireless communication systems.

In this brief, chaotic behavior and synchronization phenomena which occur in a novel Chaotic Transistors circuit with high speed operation are described. The most important point in this brief is to change a nonlinear transfer characteristic of a MOS inverter to a nonlinearity generating a chaos. The proposed circuit includes a looped MOS inverter having a pull-up resistor serially connected to a pull-down NMOS transistor. A switched capacitor (SC) circuit having a hold capacitor and two CMOS switches is added in the loop of the circuit to operate sampling holding. The chaotic behavior has been found along with a variation of a sampling clock frequency. The synchronization phenomena is also found between two coupled Chaotic Transistors circuits. The test chip is implemented employing 2 [[micro]meter] CMOS technology of MOSIS service.

Vortex motion in the mixed state portion of a superconducting flux flow transistor (SFFT) made of the high temperature superconductor, YBa2Cu3Ox, is investigated using computer simulation techniques. Results indicate that the screening current induced by the external magnetic field has little influence on the vortex motion in the link. Thus, to control SFFTs, a strong screening current must flow into the region where bias current drives vortices strongly.

Coplanar line coupled high-temperature superconducting Josephson flux-flow transistors (JFFT) are fabricated to facilitate the measurement of radio-frequency parameters in and calibrations at cryogenic temperatures of JFFT circuits. The measured parameters are in good agreement with computer-aided design simulated data for long junctions with edge injection gates.

Flux flow transistors show promise in various applications. In particular, they have been proposed for use in the interface between rapid single flux quantum circuits and silicon-based room temperature electronics. However, most models for these devices are based on discrete Josephson elements that ignore the physics of fluxoid nucleation. Numerical simulation of flux flow at the level of the Abrikosov cortex ensures the inclusion of nucleation in the models.

Class AB wide range programmable linear current mirrors in bipolar and CMOS technology are presented. Bipolar mirrors can operate with [+ or -] 0.75 V supplies, CMOS mirrors with [+ or -] 1.5 V supplies. They are characterized by having an approximately constant bandwidth that is independent of the gain adjustment. Experimental and simulation results are shown that verify the proposed structures.

Low temperature scanning electron microscopic technique is employed for the spatially resolved investigation of single-electron tunneling (SET) circuits. Signals from various parts of the circuits are imaged with the help of circuit voltage, recording as a function of the beam coordinates. Charge trapping near SET-transistor induces memory effect. The efficiency of this technique is demonstrated with a system having 11 electrons.

This paper proposes a complementary bipolar junction transistor circuit that supplies a nominally temperature invariant output current whose value is linearly related to a user defined static control voltage. The circuit developed herein is a true current source, as opposed to a current sink. It effectively functions as a static transconductor in that the controlling voltage is not limited to small signals, very little current is conducted by the controlling port, and very high static output resistance characterizes the controlled port. Moreover, the effective input-to-output transconductance is virtually independent of the absolute values of transistor parameters. Instead, its value is determined by a designable circuit resistance.

This paper presents new results concerning the stability of operating points of dc circuits. We define two classes of unstable operating points and develop criteria for identifying the class to which a given operating point belongs. We also show, by employing results from degree theory, that if a circuit possesses n structurally stable operating points (n has been shown previously to be odd), then 1/2(n - 1) of these operating points must be unstable and hence physically unobservable. A special case of this result proves that any bistable circuit must posses at least three operating points.

The ac performance issues connected with the optimization of the epitaxial silicon- and silicon-germanium-base bipolar technologies for liquid nitrogen temperature (LNT) conditions are analyzed. Results show significant developments in terms of cooling under realistic loading conditions such that dc and ac results imply the potential of bipolar technology as applied to cryogenic purposes.

A new transistor-only high-pass filter with high Q factor is proposed. The filter is realized by only four transistors. Both the Q factor and the cutoff frequency of the filter can be adjusted by control voltages.

Threshold voltage control of amorphous-silicon thin-film transistors (TFT) through hot ion implantation is experimentally studied. A threshold voltage difference of around 13 V, is attained without field-effect mobility degradation. In good agreement with numerical predictions, it is proportional to the square root of the ion implant level. The method is also used to obtain distributed-threshold voltage TFTs whose performances are also evaluated.

A self-aligned, resonant-tunneling hot electron transistor (RHET) technology is introduced for developing a full adder consisting of a three-input exclusive-OR and a three-input majority logic gate. The RHETs used have a value of 0.9 and 10 for the current gain and emitter current peak-to-valley ratio, respectively, for a common base configuration. The fabricated adder, which requires only seven RHETs, operates at 77 K.

In this paper a new effective method is developed for finding bounds on the location of all the dc solutions of the circuits containing Ebers-Moll modeled transistors and diodes. The circuit is represented by algebraic equations consisting of linear and nonlinear (exponential type) parts. The method leads to the process of successive contraction of a region including all the solutions. The crucial point of the method is weakening the nonlinearities using a real parameter which can be generally optimized. In this way it follows a very simple computation process rapidly convergent to the bounds on the solutions. An effective implementation of the method is described and numerical examples are given.

A photonic switch realized via vertical and direct integration of a heterojunction phototransistor (HPT) and a laser diode (LD) is presented. The device, which was fabricated by a liquid-phase epitaxy procedure, employs internal optical feedback between the LD and HPT while providing high gain and responsitivity at an input and output power of around 10 nW and 4 mW, respectively. A discussion of the device's switching features is also given.

The transient switching response of complementary metal oxide semiconductor (CMOS) inverters is analysed for a general formula to relate the falling output waveform to the input waveshape. Based on a first-order model of MOS device behavior, the derivations showed propagation time delay and output time constant as functionally dependent on circuit parameters. The formula was applied to a step input, a ramp input and an exponential input after which a one-dimensional macromodel was simulated for timing analysis.

This paper reviews previous theory regarding the existence and uniqueness of dc operating points possessed by bipolar transistor circuits and applies it to MOSFET circuits. Two primary results are presented. First, it is shown that certain previous topological results regarding the uniqueness of dc operating points for bipolar junction transistor and JFET circuits do not strictly hold for MOSFET circuits. Second, a two-transistor MOSFET circuit that possesses five operating points is presented. This circuit is contrasted with previous results that indicate that two-transistor BJT circuits can possess no more than three operating points. The existence of this MOSFET circuit is justified by showing how the previous result breaks down in the case of circuits containing MOSFETs. Index Terms--Bipolar transistor circuits, bistable circuits, MOSFET circuits, multivariate logic circuits, nonlinear circuits.

Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of [10.sup.5] were achieved., Semiconducting organic molecules (1) and polymers (2) can be self-assembled from solution into ordered structures with charge carrier mobilities close to that of inorganic thin-film silicon. They may form the [...]

The internal failure dynamics of the insulated gate bipolar transistor (IGBT) for unclamped inductive switching (UIS) conditions are studied using simulations and measurements. The UIS measurements are made using a unique, automated nondestructive reverse-bias safe operation area test system. Simulations are performed with an advanced IGBT circuit simulator model for UIS conditions to predict the mechanisms and conditions for failure. It is shown that the conditions for UIS failure and the shape of the anode voltage avalanche-sustaining waveforms during turn-off vary with the IGBT temperature, and turn-off current level. Evidence of single- and multiple-filament formation is presented and supported with both measurements and simulations. Index Terms--Avalanche, current constriction, failure, filament, insulated gate bipolar transistor, modeling, nondestructive testing, reverse-bias safe operation area.

The input bias current ([I.sub.IB]) of the National LM 111 voltage comparator exhibits a non-monotonic response to total dose irradiations at various dose rates. At low total doses, below 100 krad([SiO.sub.2]), increased [I.sub.IB] is due primarily to gain degradation in the circuit's input transistors. At high total doses, above 100 krad([SiO.sub.2]), [I.sub.IB] shows a downward trend that indicates the influence of compensating circuit mechanisms. Through correlation of transistor and circuit response, the transistors responsible for these compensating mechanisms are identified. Non-input transistors in the circuit's input stage lower the emitter-base operating point voltage of the input device. Lower emitter-base voltages reduce the base current supplied by the input transistors, causing a moderate 'recovery' in the circuit response.

This paper explores the possibility of constructing massively parallel computing systems using molecular electronics technology. By employing specificity of biological molecules, such as enzymes, new integrated circuit architectures which are essentially free from interconnection problems could be constructed. To clarify the proposed concept, this paper presents a functional model of a basic biomolecular switching device called an enzyme transistor. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various wire-free computing circuits can be realized. Examples described in this paper include basic analog amplifiers and digital logic circuits. This paper also presents the design of an excitable enzyme transistor circuit and demonstrates the potential of enzyme transistors for creating reaction - diffusion dynamics that performs useful computations in a massively parallel fashion. Index Terms - Molecular computing, molecular devices, nonlinear signal processing, parallel processing, pattern formation, reaction-diffusion dynamics.

Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density, circuit delay, and power consumption and is well suited for pipelined circuits. In this paper we develop a decision-diagram-based model, the 123-decision diagram, which can be used to efficiently synthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex, pipelined PTL networks using this model. Experiments on a large number of benchmark circuits show that PTL networks synthesized using our techniques are significantly more economic in terms of silicon area compared to those using existing techniques. Index Terms - Decision diagrams, logic synthesis, multilevel logic, pass transistor logic, pipelined circuits.

It could happen by the turn of the century, according to James Meindl, director of Stanford University's Center for Integrated Systems. Meindl's forecast came in the opening session of the [...]