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Deep learning techniques have recently brought many improvements in the field of neural network training, especially for prognosis and health management. The success of such an intelligent health assessment model depends not only on the availability of labeled historical data but also on the careful samples selection. However, in real operating systems such as induction machines, which generally have a long reliable life, storing the entire operation history, including deterioration (i.e. bearings), will be very expensive and difficult to feed accurately into the training model. Other alternatives sequentially store samples that hold degradation patterns similar to real ones in damage behavior by imposing an accelerated deterioration. Labels lack and differences in distributions caused by the imposed deterioration will ultimately discriminate the training model and limit its knowledge capacity. In an attempt to overcome these drawbacks, a novel sequence-by-sequence deep learning algorithm able to expand the generalization capacity by transferring obtained knowledge from life cycles of similar systems is proposed. The new algorithm aims to determine health status by involving long short-term memory neural network as a primary component of adaptive learning to extract both health stage and health index inferences. Experimental validations are performed using the PRONOSTIA bearing degradation datasets.

The recent interest in SiGe for multigate MOSFET design has demonstrated the possibility of alleviating many parasitic effects dominating at nanoscale regime. In the presented work, we focus on the performance analysis of nanoscale double gate MOSFET with a SiGe channel. The influence of introducing some structural modifications at the level of the device is shown namely the halo aspect, high-k gate stack and the dual metal gate technologies. The numerical experiments carried out using ATLAS-2D simulator confirm such enhancement with respect to a pure Si based channel device in terms of transconductance and output conductance. It is worth mentioning that other channel and gate engineering techniques deserve to be investigated in the context of SiGe multigate MOSFETs with the hope of further performance improvement

The aim of this work is to investigate the asymptotic stability of a viscoelastic Bresse system in one dimensional bounded domain. In this context, we introduce two internal damping terms expressed using the generalized Caputo fractional derivative. By adopting a diffusive representation, we show the well-posedness of the proposed system and we prove some decay results. In order to validate the theoretical findings, we implement a finite difference method and we conduct intensive numerical simulations. Moreover, we provide some insights on the convergence of the elaborated numerical scheme.

To ensure the continuity of electric power generation for photovoltaic systems, condition monitoring frameworks are subject to major enhancements. The continuous uniform delivery of electric power depends entirely on a well-designed condition maintenance program. A just-in-time task to deal with several naturally occurring faults can be correctly undertaken via the cooperation of effective detection, diagnosis, and prognostic analyses. Therefore, the present review first outlines different failure modes to which all photovoltaic systems are subjected, in addition to the essential integrated detection methods and technologies. Then, data-driven paradigms, and their contribution to solving this prediction problem, are also explored. Accordingly, this review primarily investigates the different learning architectures used (i.e., ordinary, hybrid, and ensemble) in relation to their learning frameworks (i.e., traditional and deep learning). It also discusses the extension of machine learning to knowledge-driven approaches, including generative models such as adversarial networks and transfer learning. Finally, this review provides insights into different works to highlight various operating conditions and different numbers and types of failures, and provides links to some publicly available datasets in the field. The clear organization of the abundant information on this subject may result in rigorous guidelines for the trends adopted in the future.

Condition monitoring (CM) of industrial processes is essential for reducing downtime and increasing productivity through accurate Condition-Based Maintenance (CBM) scheduling. Indeed, advanced intelligent learning systems for Fault Diagnosis (FD) make it possible to effectively isolate and identify the origins of faults. Proven smart industrial infrastructure technology enables FD to be a fully decentralized distributed computing task. To this end, such distribution among different regions/institutions, often subject to so-called data islanding, is limited to privacy, security risks, and industry competition due to the limitation of legal regulations or conflicts of interest. Therefore, Federated Learning (FL) is considered an efficient process of separating data from multiple participants to collaboratively train an intelligent and reliable FD model. As no comprehensive study has been introduced on this subject to date, as far as we know, such a review-based study is urgently needed. Within this scope, our work is devoted to reviewing recent advances in FL applications for process diagnostics, while FD methods, challenges, and future prospects are given special attention.

In the last few years, an accelerated trend towards the miniaturization of nanoscale circuits has been recorded. In this context, the Tunneling Field-Effect Transistors (TFETs) are gaining attention because of their good subthreshold characteristics, high scalability and low leakage current. However, they suffer from low values of the ON-state current and severe ambipolar transport mechanism. The aim of this work is to investigate the performance of SiGe nanoscale Double Gate TFET device including low doped drain region. The electrical performance of the considered device is investigated numerically using ATLAS 2D simulator, where both scaling and reliability aspects of the proposed design are reported. In this context, we address the impact of the channel length, traps density and drain doping parameters on the variation of some figures of merit of the device namely the swing factor and the ION/IOFF ratio. The obtained results indicate the superior immunity of the proposed design against traps induced degradation in comparison to the conventional TFET structure. Therefore, this work can offer more insights regarding the benefit of adopting channel materials and drain doping engineering techniques for future reliable low-power nanoscale electronic applications.

In this work, thin films of aluminum doped ZnO (AZO) were deposited on ultrasonically cleaned glass substrates by sol-gel process using dip and spin coating techniques. For this purpose, Zinc acetate dihydrate, aluminum nitrate nonahydrate, ethanol and mono ethanolamine were employed as precursor, dopant, solvent and stabilizer, respectively. X-ray diffraction, UV–vis, photoluminescence, 4-point probe and Van der pauw techniques were investigated for the characterization of the prepared AZO thin films. X-ray-analysis revealed that all the prepared films have hexagonal wurtzite structure with a relative preferential orientation along the c-axis and the lattice parameters are close to the standard values reported in literature. UV–vis spectroscopy showed that the average value of the films’ transmittance in the visible region is found to be around 85% and the gap ranges in the interval [3.15 eV–3.30 eV]. The photoluminescence spectrum only showed the UV peak while the broad band of the visible region was completely vanished. The electrical measurements indicate that sol-gel methods provide relatively high resistivities compared to those obtained with physical vapor deposition (PVD) techniques.

A semianalytical model based on a nonlocal approach is proposed for an undoped tunnel field-effect transistor (TFET) with a vertical surrounding-gate structure. The heterostructure band alignment is computed by applying the affinity rule on suitable potential expressions obtained from the two-dimensional (2-D) electrostatic solution for all device regions. The fringing field, doping-induced degeneracy, ambipolarity, and dual modulation effects are included with the aim of obtaining a large domain of validity. The core model is completed with expressions for the capacitance of the terminals and validated against numerical simulations obtained using ATLAS-2D software. An investigation of the types of band alignment and the impact of doping on the device performance is also conducted. The developed models could be implemented into commercial simulators to investigate circuits based on such multigate field-effect transistors (FETs).

In the last years, predictive maintenance has gained a central position in condition-based maintenance tasks planning. Machine learning approaches have been very successful in simplifying the construction of prognostic models for health assessment based on available historical labeled data issued from similar systems or specific physical models. However, if the collected samples suffer from lack of labels (small labeled dataset or not enough samples), the process of generalization of the learning model on the dataset as well as on the newly arrived samples (application) can be very difficult. In an attempt to overcome such drawbacks, a new deep supervised learning approach is introduced in this paper. The proposed approach aims at extracting and learning important patterns even from a small amount of data in order to produce more general health estimator. The algorithm is trained online based on local receptive field theories of extreme learning machines using data issued from a propulsion system simulator. Compared to extreme learning machine variants, the new algorithm shows a higher level of accuracy in terms of approximation and generalization under several training paradigms.

The degradation aspects associated with Tunneling Field-Effect Transistors (TFETs) have become an active research area that needs further development. In this work, a new computation methodology based on an adaptive neuro-fuzzy inference system (ANFIS) is proposed for predicting the switching capabilities of Gate All Around (GAA) TFET devices including interface trap effects. Accordingly, several performance criteria including the current ratio (Ion/Ioff) ratio and the swing factor (S) are considered to analyze the device degradation phenomenon. ATLAS 2-D numerical simulator has been exploited for the elaboration of the training dataset of the neuro-fuzzy system. Based on the obtained outcomes, the proposed approach can provide new pathways for accurately predicting the performance of nanoelectronic circuits based on GAA-TFETs including the ageing effects.

In this paper, a novel Infrared (IR) sensor based on Junctionless (JL) Germanium optically controlled gate (OC) Tunneling-FET phototransistor is proposed and numerically investigated. An exhaustive study concerning the working mechanism of the proposed device is carried out using 2-Dimuntional ATLAS device simulator taking into account the band-to-band tunneling transport model. The optoelectronic properties of the proposed JL-OC-TFET are also analyzed, where its IR photoresponse, switching and detectivity characteristics are reported. In addition, comparative performance analysis between the conventional OC FET-based devices and our proposed one is carried out by extracting their Figures of Merit (FoM) parameters including responsivity, ION/IOFF ratio and the optical gain. It is found that the proposed JL-OC-TFET outperforms considerably the conventional IR-sensors in terms of the device FoM, offering a high relative improvement exceeding 220%. Therefore, this investigation can offer new exciting opportunities regarding the advantage of using JL tunneling devices for the potential improvement of nowadays optoelectronic systems.

In the last recent years, a large community of researchers and industrial practitioners has been attracted by combining different prognostics models as such strategy results in boosted accuracy and robust performance compared to the exploitation of single models. The present work is devoted to the investigation of three new fusion schemes for the remaining useful life forecast. These integrated frameworks are based on aggregating a set of Gaussian process regression models thanks to the Induced Ordered Weighted Averaging Operators. The combination procedure is built upon three proposed analytical weighting schemes including exponential, logarithmic and inverse functions. In addition, the uncertainty aspect is supported in this work, where the proposed functions are used to weighted average the variances released from competitive Gaussian process regression models. The training data are transformed into gradient values, which are adopted as new training data instead of the original observations. A lithium-ion battery data set is used as a benchmark to prove the efficiency of the proposed weighting schemes. The obtained results are promising and may provide some guidelines for future advances in performing robust fusion options to accurately estimate the remaining useful life.

In this paper, a new nanoscale double-gate junctionless tunneling field-effect transistor (DG-JL TFET) based on a Si1−xGex/Si/Ge heterojunction (HJ) structure is proposed to achieve an improved electrical performance. The effect of introducing the Si1−xGex material at the source side on improving the subthreshold behavior of the DG-JL TFET and on suppressing ambipolar conduction is investigated. Moreover, the impact of the Ge mole fraction in the proposed Si1−xGex source region on the electrical figures of merit (FoMs) of the transistor, including the swing factor and the ION/IOFF ratio is analyzed. It is found that the optimized design with 60 atom % of Ge offers improved switching behavior and enhanced derived current capability at the nanoscale level, with a swing factor of 42 mV/dec and an ION/IOFF ratio of 115 dB. Further, the scaling capability of the proposed Si1−xGex/Si/Ge DG-HJ-JL TFET structure is investigated and compared to that of a conventional Ge-DG-JL TFET design, where the optimized design exhibits an improved switching behavior at the nanoscale level. These results make the optimized device suitable for designing digital circuit for high-performance nanoelectronic applications.

A continuous and accurate model based on the two-dimensional (2D) potential solution of a tunnel field-effect transistor (TFET) with undoped vertical surrounding-gate (VSG) structure is proposed. Both ambipolarity and dual modulation effects are included to obtain a more accurate analytical model, whose validity is demonstrated by comparison with two-dimensional numerical simulations using ATLAS-2D. The continuity of the proposed model enables extraction of analog/radiofrequency (RF) parameters and device figures of merit. Moreover, the effect of introducing a high- $$\kappa $$ layer on the gate oxide in improving the behavior of the VSG-TFET is explored for use in high-performance analog/RF applications. The proposed continuous analytical model can be easily implemented in commercial simulators to study and investigate VSG-TFET-based nanoelectronic circuits.

The estimation of average lifetime has been considered as a serious reliability concern for VLSI components. However, with the tremendous downscaling of MOSFET devices, it becomes very difficult to predict such measure with satisfactory precision due to the amplified parasitic effects at the deep scale level. The present work aims at investigating the efficiency of adaptive neuro-fuzzy inference system approach as a predictor of junctionless gate all around MOSFET device lifetime. Our predictions are compared versus the numerical results obtained by ATLAS simulator, where a good agreement is obtained.

Recently, the Junctionless Double Gate MOSFET with source/drain extensions has proved competitive performance measures due to the reduction of the series resistance between the metal contacts and source/drain regions. However, the precise modeling of different response functions is still an important issue especially at nanoscale level because of the inclusion of complex phenomena such as quantum transport mechanisms and hot carrier degradation effect. In this perspective, our aim in the presented work is to investigate the efficiency of a novel approach based on Kriging metamodeling and multi-objective particle swarm optimization for the exploitation of the considered device in terms of some analog/RF performances. Data generated by ATLAS-2D simulator, are used to establish Kriging metamodels for the Gain and Transconductance Generation Factor. It is highlighted that the obtained models can be used accurately in a multi-objective context to offer several Pareto optimal configurations. As a result, a wide range of biasing configurations is available to the designer depending on imposed constraints.

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

The use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the nanoscale multi-gate junctionless MOSFETs. Therefore, new designs and accurate investigation of nanoscale double gate junctionless (DGJ) MOSFET including the defects at the interface Si/SiO2 are required for the comprehension of the fundamentals of such device behavior against the ageing phenomenon. Based on 2D numerical investigation of a nanoscale DGJ MOSFET, in the present work a numerical study for I-V and small signal characteristics, by including both the highly doped extension regions and the interfacial defects, is presented. The investigated design, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the device immunity against the interfacial defects under critical conditions, where the channel length is taken equals to 10 nm. In this context, I-V, analog and linearity characteristics are investigated by an appropriate 2-D numerical modeling, where the obtained results are compared with those of the conventional DGJ MOSFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits.

Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the high series resistance associated to the source and drain extensions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. In the present paper, a numerical investigation for the drain current and small signal characteristics is conducted for the DGJ MOSFET by including highly doped extension regions. The proposed approach, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current, small signal parameters, analog/RF behavior and linearity of DGJ MOSFET for high performance analog applications. In this context, I – V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics.

In this paper, we present a comprehensive investigation the impact of various high-k gate materials on both breakdown voltage and drain current of a vertical 4H-SiC-based power MOSFET, operating in the quasi-saturation regime. The device electrical behavior is numerically investigated using a TCAD-based computation provided by ATLAS 2D simulator. Moreover, the performance parameters, governing the power MOSFET breakdown characteristics are extracted in order to reveal the role of the high-k gate materials in improving the transistor electrical performance. The effect of the dielectric permittivity on the derived current capability in also analyzed. After, we conduct a sensitivity analysis of the breakdown voltage with several high-k materials (Al2O3, HfSiO4, HfO2, and TiO2) and different dielectric thicknesses. It is found that the proposed power MOSFET design exhibits improved electrical behavior not only enables enhancing the drain current but also allows achieving superior breakdown performance as compared to the conventional design, making it suitable for high-performance power electronic applications.

This paper shows a new Double Gate Junctionless (DGJL) MOSFET design based on both highly doped drain/source extensions and gate material engineering. The device electrical behavior at the nanoscale level is investigated using an accurate numerical computation based on TCAD simulation provided by ATLAS 2D simulator, where quantum confinement effects and the modified drift-diffusion transport model that takes into account SCEs are included. Circuit performance parameters are also developed incorporating the impact of dual-material gate engineering and highly doped extension regions. The effect of the proposed design amendments on the performance of the common source single stage amplifier circuit based on DGJL MOSFET is also performed, where the proposed design exhibits an outstanding capability for offering improved amplifier properties. In order to analyze the characteristics and circuit performance of the device, we have adopted mixed mode simulation under Silvaco environment for the implementation of the inverter circuit. Based on the numerical, outcomes satisfactory results are recorded in comparison with the conventional nanoscale junctionless design.

The SiGe-based alloy is considered as one of the most promising materials for reliable and high performance microelectronic devices. The use of a lower band-gap material in the channel region of the MOSFET, such as SiGe, is a potential candidate given their compatibility with the process developed for pure Si-based devices. Moreover, the important increasing in the drain current due to the increased electrons mobility in SiGe material is expected. However, the growth of this material is not totally controlled, and the presence of defects is more than expected after a growth run of this material. Therefore, in order to obtain a global view of SiGe-based nanoscale Double Gate (DG) MOSFET performance under critical conditions, numerical modeling of nanoscale SiGe DG MOSFET including Interfacial defect effects (SiGe/Si) is indispensable for the comprehension of the fundamentals of such device characteristics. Based on numerical investigation of a nanoscale SiGe DG MOSFET, including the defects in the interface region, in the present paper a numerical model for I-V and small signal characteristics by including the interfacial defects, after considering the uniform function approximation for the interface defects distribution at the drain side, is developed to explain the immunity behavior of the nanoscale SiGe-based transistor against the defect densities. In this context, DC and RF characteristics of the proposed design are analyzed by 2-D numerical simulation and compared with conventional Si DG MOSFET characteristics. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

To improve the electrical performance and reduce the fabrication cost of the solar cell, thin-film solar-cell concepts are widely explored. In this context, many studies have been carried out to study the impact of the thin thickness of the material on the solar cell behavior. Recently, the Si1-xGex/Si heterostructure is considered as attractive alternative for photovoltaic applications due to their band structures, which allow getting an additional gain in the device efficiency. However, the growth of this material is not totally controlled, and the presence of interfacial defects is more than estimated after a growth run of this material. Therefore, new experimental and numerical investigations which capture the Si1-xGex/Si heterostructure behavior should be developed in order to build a complete Si1-xGex/Si-based solar cell model for photovoltaic applications. In this paper, we aim at highlighting the immunity of the Si1-xGex/Si heterostructure against the defects degradation effect at nanoscale level (thin films). The effect of interface defect on the heterostructure has been carried out by extensive simulation using Atlas 3-D simulator, including the device dimension and the Ge Mole fraction effects.

This paper is devoted to the presentation of a quantitative analysis of the Junctionless Gate All Around RADFET (JL GAA RADFET) dosimeter, where the numerical simulation has been carried out using the Atlas 3-D simulator. The impact of the total dose, alternative gate materials and the channel doping on the threshold voltage of the JL GAA RADFET is addressed. The obtained results have indicated a significant improvement in the subthreshold parameters when compared to the conventional GAA RADFET dosimeter. Therefore, the implementation of junctionless-based sensors in the near future can provide more accurate results with low costs, in addition to alleviating many difficulties in the measurement procedure. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this paper, we propose a numerical investigation based framework for the analysis of a new MOSFET device, which is motivated by gate engineering and junctionless channel paradigms. The device immunity against the hot carrier effect is evaluated by comparing the obtained relative degradation in the threshold voltage to its counterparts in the conventional and single junctionless double gate MOSFETs. It is found that our proposed design can efficiently deal with the hot carrier and short channel effects. As a result, the gate-engineering-based design for junctionless channel structures appears to be of potential importance in the development of nanoscale devices dedicated to digital circuit applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this chapter, we consider the single machine scheduling problem including uncertain parameters and position based learning effect with the aim to minimize the weighted sum of jobs completion times. Due to the ill-known quantities within the model, the determination procedures of optimal solutions in the conventional way is not an affordable task and more elaborated frameworks should be developed. In this context, we introduce two solution approaches for the proposed fuzzy scheduling problem in order to obtain an exact or a satisfactory near optimal solution. The first approach is based on the extension of the well-known Smith’s rule resulting in a polynomial algorithm with a complexity O(n l o g(n)). However, a severe constraint on jobs (fuzzy agreeability concept) should be satisfied in this case. The second approach based on optimization methods is built upon the assumption of unequal fuzzy release dates in addition to the absence of fuzzy agreeability constraint. Three trajectory based metaheuristics (Simulated annealing, taboo search and kangaroo search) are implemented and applied to solve the resulting problem. For the proposed methods throughout the chapter, several numerical experimentations jointly with statistical deductions are provided.

This paper deals with the immunity behavior of the junctionless DG MOSFET device against the hot carrier degradation effect. The junctionless device is highly privileged because of its easy fabrication procedure, homogeneity along the channel axe in addition to its promising electrical characteristics compared to the conventional DG MOSFET with PN junction at the source and the drain sides. As a result, we demonstrate that junctionless DG MOSFET can be a viable option to enhance the immunity performances of nanoscale CMOS-based devices technology for nanoelectronics digital applications (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)