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1. The PLATO Mission

2. Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs

3. Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors

6. Advancements and evolution of PLATO's instrument control unit: insights from engineering model performance testing to qualification model development

7. The instrument control unit of the PLATO payload: design consolidation following the preliminary design review by ESA

8. A combined software and hardware data compression approach in PLATO

10. The instrument control unit of the PLATO payload: design consolidation following the preliminary design review by ESA

12. Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

14. Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

16. Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA

18. Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

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