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In this paper, we proposed an architecture of embedded systems for high-frame-rate real-time vision on the order of 1000 f/s, which achieved both hardware reconfigurability and easy algorithm implementation while fulfilling performance demands. The proposed system consisted of an embedded microprocessor and field programmable gate arrays (FPGAs). A coprocessor consisting of memory units, direct memory access controller units, and image processing units were implemented in each FPGA. While the number of units and functions are reconfigurable by reprogramming the FPGAs, users can implement algorithms without hardware knowledge. A descriptor method in which the central processing unit gave instructions to each coprocessor through a register array enabled task-level parallel processing as well as pixel-level parallel processing in the processing units. The specifications of an evaluation system developed based on the proposed architecture, the results of performance evaluation, and application examples using the system were shown.

We demonstrate surface-image synthesis of moving, spinning cylindrical objects using a commercially available high-speed area scan camera. The frame rate used in the demonstration experiment was 1,000 fps, which is sufficient to achieve surface-image synthesis of cylinders spun at up to 36 rps. We successfully demonstrated a technique based on an algorithm similar to image mosaicing at 1,000 fps, for the first time to the best of our knowledge. In this paper, we discuss techniques to overcome the potential problems faced when applying surface-image synthesis to cylindrical objects, such as image distortion, quantization errors due to superimposing images, and intensity variations due to the surface curvature. An FPGA-based parallel image processing board, PB-1, that we developed was used to implement these demonstrations. We introduce this application of PB-1 as a potential practical solution to the long-standing problem of industrial visual inspection using real-time high-speed vision.

Reconfigurable Fourier plane computer generated holograms are implemented by optically reducing a binary hologram image from an electrically addressed spatial light modulator onto a phase-only optically addressed spatial light modulator. Holograms with 400 × 400 14 μm pixels are obtained and the experimental performances of holograms designed by different design algorithms are compared.

The design of an optoelectronic parallel processing system is presented. In this system a reconfigurable computer-generated hologram is used to perform a shift-invariant optical interconnection operation. Scalability issues are investigated, and simple cellular processing operations are experimentally demonstrated.