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This paper describes the potential of tunable strain in field-effect transistors to boost performance of digital logic. Voltage-controlled strain can be imposed on a semiconductor body by the integration of a piezoelectric material improving transistor performance. In this paper, we derive the relations governing the subthreshold swing in such devices to improve the understanding. Using these relations and considering the mechanical and technological boundary conditions, we discuss possible device architectures that employ this principle. Further, we review the recently published experimental and modeling results of this device, and give analytical estimates of the power consumption.

This paper describes the potential of tunable strain in field-effect transistors to boost performance of digital logic. Voltage-controlled strain can be imposed on a semiconductor body by the integration of a piezoelectric material improving transistor performance. In this paper, we derive the relations governing the subthreshold swing in such devices to improve the understanding. Using these relations and considering the mechanical and technological boundary conditions, we discuss possible device architectures that employ this principle. Further, we review the recently published experimental and modeling results of this device, and give analytical estimates of the power consumption.

We report on a feature for the transistor, a piezoelectric layer to modulate the strain in the channel. The strain is proportional to the gate-source voltage, and thus increases as the device is turned on. As a result, the device has the leakage current of a relaxed device and the lower threshold voltage of a strained device. Our results, obtained by combining electrical and mechanical simulations, demonstrate that strain modulation can result in a 9 mV/decade smaller subthreshold swing for a FinFET.

In this paper we demonstrate a method to extract the electric field dependence of first order piezoelectric parameters. We fit the Mason model to measured frequency dependent electrical impedance data of aluminum-nitride bulk acoustic wave resonators for various DC biasing. The impedance was fitted accurately at the mechanical resonances and in the quasi-static regime well below the resonance frequency. This revealed the dependence of the piezoelectric stiffness, charge constant, and permittivity on the electric field. From this the four second order piezoelectric parameters were calculated.

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

In this work we will provide the results of an investigation into electron and hole mobility at high inversion charge density (6 to 8x1012 cm-2) in TiN/HfO2/SiOx/Si MOSFETs. We examine the influence of oxide charge on carrier mobility by using temperature bias stress to deliberately increase the density of oxide charge in the HfO2/SiOx gate stack. The temperature dependence of the electron mobility (50 K to 350 K) and hole mobility (218 K to 373 K) is determined before and after the various levels of oxide and interface degradation to allow an experimental determination of the Coulomb scattering term (α) as a function of temperature for various oxide charge levels. Based on the temperature dependant α determined for a 3nm HfO2 gate thickness n channel MOSFET, an empirical model has been developed which accurately predicts the measured electron mobility for the 2.4, 2.0 and 1.6nm HfO2 gate thicknesses.

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