37 results on '"Todman, Tim"'
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2. In-Circuit Assertions and Exceptions for Reconfigurable Hardware Design
3. Self-aware Hardware Acceleration of Financial Applications on a Heterogeneous Cluster
4. Self-adaptive Hardware Acceleration on a Heterogeneous Cluster
5. The hArtes Tool Chain
6. Custom Instructions for Networked Processor Templates
7. Smart Enumeration: A Systematic Approach to Exhaustive Search
8. Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation
9. Non-deterministic event brokered computing
10. Methods and Tools for High-Resolution Imaging
11. Custom enhancements to networked processor templates
12. Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms
13. Customisable Hardware Compilation
14. Exploring performance enhancement of event-driven processor networks
15. Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies
16. Methods and Tools for High-Resolution Imaging
17. Lossy Multiport Memory
18. Transparent In-Circuit Assertions for FPGAs
19. DeepPump: Multi-pumping deep Neural Networks
20. EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures
21. In-circuit temporal monitors for runtime verification of reconfigurable designs
22. Transparent insertion of latency-oblivious logic onto FPGAs
23. Using Statistical Assertions to Guide Self-Adaptive Systems
24. In-circuit temporal monitors for runtime verification of reconfigurable designs.
25. Runtime assertions and exceptions for streaming systems
26. Optimizing Hardware Design by Composing Utility-Directed Transformations
27. Verification of streaming hardware and software codesigns
28. Verification of streaming designs by combining symbolic simulation and equivalence checking
29. Reconfigurable Design Automation by High-Level Exploration
30. Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms
31. Convex models for accelerating applications on FPGA-based clusters
32. Customizable Composition and Parameterization of Hardware Design Transformations
33. Automatic optimisation of MapReduce designs by geometric programming
34. Optimising designs by combining model-based and pattern-based transformations
35. Optimal implementation of combinational logic on look-up tables
36. Improving Bounds for FPGA Logic Minimization
37. Combining optimizations in automated low power design.
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