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6 results on '"Timing failures"'

1. Predicting Timing Failures in Web Services

Author

Laranjeiro, Nuno, Vieira, Marco, Madeira, Henrique, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Chen, Lei, editor, Liu, Chengfei, editor, Liu, Qing, editor, and Deng, Ke, editor

Published
2009
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2. Timing Error Tolerance in Small Core Designs for SoC Applications.

Author

Valadimas, Stefanos, Tsiatouhas, Yiorgos, and Arapoyanni, Angela

Subjects
*ERROR analysis in mathematics, *ENGINEERING tolerances, *SYSTEMS on a chip, *RELIABILITY in engineering, *ELECTRIC potential, *INTEGRATED circuits
Abstract

Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage\frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip-flop. The proposed solution is characterized by very low silicon area and power requirements compared to previous design schemes in the open literature. To validate its efficiency, it has been applied in the design of a MIPS microprocessor core in a 90 nm technology, while a demonstration version of the same core in an FPGA platform is presented. [ABSTRACT FROM AUTHOR]

Published
2016
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3. Model-driven estimation approach for system reliability using integrated tasks and resources.

Author

Isa, Mohd, Jawawi, Dayang, and Zaki, Mohd

Subjects
COMPUTER software development, SOFTWARE engineering, EMBEDDED computer systems, MODEL-driven software architecture, COMPUTER software industry
Abstract

The increasing complexity of software systems in embedded systems or industrial business domains has led to the importance of reliability analysis for current systems. Reliability analysis has become a crucial part of the system development life cycle, and a new approach is needed to enable an early analysis for reliability estimation, especially for the system under design. However, the existing approach neglects the correlation between system resource and system task for estimating system reliability. This subsequently restricts accuracy of the estimation as well as causing difficulties in identifying critical resources and tasks during the design phase. This paper proposes a model-driven system reliability estimation using a scenario-based approach to estimate system reliability and identify its critical resources and system tasks during the design phase. This model is based on the PerFAM model, which can specifically view timing failures through a system scenario. The proposed approach is validated by the application of a sensitivity analysis into one case study. The case study demonstrates an essential relationship between system reliability, as well as both resources and tasks, which ultimately becomes the integral part for a system reliability estimation assessment. [ABSTRACT FROM AUTHOR]

Published
2014
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4. Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

Author

Chakraborty, Ashutosh, Duraisami, Karthik, Sithambaram, Prassanna, Macii, Alberto, Macii, Enrico, and Poncino, Massimo

Subjects
*INTEGRATED circuits, *EMBEDDED computer systems, *ALGORITHMS, *INTEGRATED circuit interconnections, *ELECTRONIC circuits
Abstract

Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliability and robustness to failures of nanometer integrated circuits. In fact, signal propagation on interconnects slows down as temperature rises; for long wires crossing regions at different temperatures, such as the clock network, thermally induced delay and skew get altered and may result in timing faults. Failures of this kind are difficult to face due to their transient nature. This paper focuses on clock tree design for the class of embedded systems-on-chip with spatially nonuniform but temporally stationary thermal profiles. We contribute two algorithms for the thermal-aware clock network design that take into account on-chip temperature variations of this nature. The experimental results that we have collected on a number of examples and for different thermal profiles show that, in the presence of on-chip spatial temperature gradients, clock trees designed using a standard methodology incur very significant skew violations, thus originating circuit failures. Instead, clock networks designed using the algorithms presented in this paper always satisfy the initial skew bound. [ABSTRACT FROM PUBLISHER]

Published
2010
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5. Fine-grain analysis of the parameters involved in aging of digital circuits

Author

Olivier Heron, Chiara Sandionigi, Boukary Ouattara, Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA))

Subjects
Timing failures, Engineering, Systems analysis, 02 engineering and technology, Integrated circuit, 01 natural sciences, Bottleneck, law.invention, [SPI]Engineering Sciences [physics], Reliability (semiconductor), law, 0103 physical sciences, Timing circuits, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Register-transfer level, 010302 applied physics, Digital electronics, business.industry, Mixed-signal integrated circuit, Digital circuits, Fine-grain analysis, Circuit extraction, 020202 computer hardware & architecture, Reliability engineering, business, Electric network analysis, Design time, Asynchronous circuit
Abstract

Conference of 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 ; Conference Date: 4 July 2016 Through 6 July 2016; Conference Code:124500; International audience; Integrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits.

Published
2016

6. XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests

Author

Trinadh, A.S., Potluri, S., Balachandran, S., Babu, Ch.S., Kamakoti, V.

Subjects
Algorithms, Design for testability, Filling, Flip flop circuits, Integrated circuit testing, Testing, Capture-power reductions, Large designs, Peak capture-power, Peak power minimizations, Scan-based testing, Test power reduction, Test vector ordering, Timing failures, Electric losses
Abstract

Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failures. Since test power dissipation is typically higher than functional power, test peak power minimization becomes very important in order to avoid test induced timing failures. Test cubes for large designs are usually dominated by don't care bits, making X-leveraging algorithms promising for test power reduction. In this paper, we show that X-bit statistics can be used to reorder test vectors on scan based architectures realized using toggle-masking flip flops. Based on this, the paper also presents an algorithm namely balanced X-filling that when applied to ITC'99 circuits, reduced the peak capture power by 7.4% on the average and 40.3% in the best case. Additionally XStat improved the running time for Test Vector Ordering and X-filling phases compared to the best known techniques. Copyright � 2014 American Scientific Publishers

Published
2014

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