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In this brief, we reported the improved break-down reliability and endurance in 10-nm Hf $_{0.5}$ Zr $_{0.5}$ O₂(HZO) using grain boundary interruption. By inserting an amorphous Al₂O₃ layer in the middle of polycrystalline HZO, grain boundaries penetrating between the electrodes were interrupted. Compared with single-layer HZO [metal-ferroelectric-metal (MFM)] and HZO/Al₂O₃ [metal-ferroelectric-insulator-metal (MFIM)], the ferroelectric/insulator/ferroelectric [metal-ferroelectric-insulator-ferroelectric-metal (MFIFM)] structure exhibited 9x reduction of leakage current, 0.85-V increase of breakdown (BD) voltage ( $T_{BD}$ ), and 0.97-V increase of voltage for 10-year time-dependent dielectric breakdown (TDDB) lifetime. Furthermore, >10¹⁰ endurance was achieved in MFIFM capacitor, which has more than three orders of magnitude improvement than MFM and MFIM capacitor. This work provides an effective way to enhance the reliability of HZO-based ferroelectric devices.

Despite the remarkable development in ferroelectric HfO2-based FETs, key reliability challenges (e.g., retention, endurance, etc.) may still limit their widespread adoption in memory and logic applications. In this paper, we present a simple theoretical framework—based on the Landau theory of phase transition—to design both ferroelectric FETs (FeFETs) and negative capacitance transistors (NCFETs) and investigate their reliability issues. For FeFETs, we analyze the role of interface and bulk traps on memory window closure to quantify endurance under different operating conditions. For NCFETs, we discuss the beneficial role of NC effect in reducing (or even eliminating) the persistent reliability issue of negative bias temperature instability that has plagued MOSFETs for decades. FE/NCFETs can also be affected by the Hot Atom Damage involving switching-induced bond dissociation during transient overshoot. We conclude by discussing how other FET reliability issues (e.g., TDDB, HCD, etc.) may also have to be reinterpreted for FE/NCFETs.

Extensive use of electronic components in mission critical applications has brought reliability concerns in VLSI to the forefront. Ageing related reliability effects such as Time Dependent Dielectric Breakdown (TDDB) might lead to in-field chip failures, thereby degrading the functional safety of the modules. Thus, on-chip monitoring and fast characterization of these ageing phenomenon are gaining prominence. MOSFET Gate leakage current monitoring provides a means to characterize and monitor Time Dependent Dielectric Breakdown (TDDB). This brief presents a fast, large dynamic range, monolithic gate current monitor with a digital output. The circuit does not require an explicit ADC, provides a dynamic range from 200pA to $1~\mu \text{A}$ and requires 1–2 clock cycles of measurement time for most of the device lifetime. Working of the circuit has been demonstrated using Cadence Spectre/AMS simulations.

In this work, we present the substrate bias enhanced trap effects on time-dependent dielectric breakdown (TDDB) in GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) by experiment. Under different substrate biases, the shape parameter $\beta $ and scale factor $\eta $ of the Weibull distribution are extracted from the experimental data. A monotonical decrease in $\beta $ from intrinsic breakdown to extrinsic breakdown relating to the hole-emission from the acceptor-like buffer traps with increased negative substrate biases has been observed, while $\eta $ is increased at large positive substrate biases. This unexpected increase in $\eta $ suggests that the donor-like buffer traps play an important role with a longer lifetime. The trap mechanisms, relating to percolation path establishment, are analyzed based on progressive breakdown (PBD). The capacitance–voltage characteristics are measured during each stress cycle confirming the hole fluence and electron injection in the gate-stack layer with different trap distributions under various substrate biases. Finally, 2-D device simulations are carried out to probe for physical insight into the traps on TDDB failure mechanisms.

Silicon-carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFETs) are core devices for future power electronics. The factors limiting their automotive applications are currently under investigation. Postoxidation annealing in NO gas is a key technology to achieving high carrier mobility in SiC-MOSFETs. In this article, we study the NO annealing effects on time-dependent dielectric breakdown (TDDB) reliability by the constant voltage stress (CVS) method at room temperature (RT). We show that heavy NO annealing enhances hole trapping near the SiO2/SiC interface and leads to a rapid increase in the gate current ( $I_{\text {g}}$ ) and results in shorter time-to-breakdown ( $t_{\text {BD}}$ ) and smaller Weibull slope of $t_{\text {BD}}$ in comparison to light NO annealing case. However, the detailed examination of the $I_{\text {g}}$ behavior reveals that the charge-to-breakdown ( $Q_{\text {BD}}$ ) and its distribution do not deteriorate. Therefore, we must reconsider the use of the CVS method by examining the $I_{\text {g}}$ behavior during stress, which strongly depends on NO annealing conditions.

It is widely believed that the fatigue process of ferroelectric HfZrO (HZO) film is a permanent damage and unrecoverable, which can be regarded as a Time Dependent Dielectric Breakdown (TDDB) process. In this work, the fatigue process of HZO film under low-electric field is found to be irrelevant to defect generation. Furthermore, this fatigued device can be recovered by higher voltage stimulus and then switch normally with lower voltage pulses. This observed recoverable fatigue process is systematically investigated by the conductance method and the first-order reversal curve (FORC) measurement and the mechanism is attributed to electron de-trapping. This observed recoverable fatigue process gives the new insights on the endurance failure mechanism of HZO film under low-electric field.

In this paper, we report a 1.84 kV GaN-on-GaN Schottky barrier diode (SBD) corresponds to a low on-resistance of 1.98 mΩ-cm2. The GaN epi-layer was etched to the multi-fins-structure with optimized bevel angle. The fins structure enables to improve the breakdown voltage by means of the uniforme electric field distribution. Afterwards, the GaN fins were capped by atomic layer deposition (ALD)-grown AlN film. The AlN served as a tunneling-barrier layer, which not only passivated the GaN surface but also decreased the turn-on voltage. The AlN-capped SBD shows a turn-on voltage at 0.18 V. Furthermore, the temperature-dependent transfer characteristics suggest the different current tunneling mechanisms at low and high electric field conditions, respectively. The time-dependent dielectric breakdown (TDDB) measurement suggests the surface traps were well passivated by ALD-AlN, which implies that the AlN cap-layer enables to improve the device reliability.

Increasing demands for mass storage and new paradigm computing ask for non-volatile memories that can meet reliability requirements. Hf0.5Zr0.5O2-based (HZO) memory has attracted growing attention due to its excellent CMOS compatibility. This letter investigated the time dependent dielectric breakdown (TDDB) of HZO ferroelectric under both forward and reverse stress conditions, which is relevant to the memory’s practical operation. The key similarities and the differences for both breakdown conditions have been identified and the underlying mechanism is explored. It is found that the pre-existing oxygen vacancies near the bottom electrode play the key role and all the observed phenomenon can be explained. Therefore, the precise control of these pre-existing oxygen vacancies can be critical for future TDDB improvement.

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( $\gamma $ ) are observed at oxide electric fields ( $E_{ox}$ ) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields ( $E_{ox}= {\mathrm {8 MV/cm}}$ and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated $t_{63\%}$ lifetimes (times to 63% failures) from TDDB measurements performed at $E_{ox} < {\mathrm {8.5 MV/cm}}$ are longer than 108 hours at 150°C for all vendors. The predicted lifetimes at $E_{ox}= {\mathrm {4 MV/cm}}$ demonstrate more than 105 times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.

Hafnium zirconium silicon oxide ((HfZrO4)1−x(SiO2)x) materials were investigated through the defect analysis and reliability characterization for next generation high-κ dielectric. Silicate doped hafnium zirconium oxide (HfZrO4) films showed a reduction of negative flat-band voltage (Vfb) shift compared to pure HfZrO4. This result was caused by a decrease in donor-like interface traps (Dit) and positive border traps (Nbt). As the silicon oxide (SiO2) content increased, the Vfb was shifted in the positive direction from −1.23 to −1.10 to −0.91 V and the slope of the capacitance–voltage (C–V) curve increased. The nonparallel shift of the C–V characteristics was affected by the Dit, while the Nbt was responsible for the parallel C–V curve shift. The values of Dit reduced from 4.3 × 1011, 3.5 × 1011, and 3.0 × 1011 cm−2eV−1, as well as the values of Nbt were decreased from 5.24, 3.90 to 2.26 × 1012 cm−2. Finally, reduction of defects in the HfZrO4-base film with an addition of SiO2 affected the gate oxide reliability characteristics, such as gate leakage current (JG), bias temperature stress instability (BTSI), and time dependent gate dielectric breakdown (TDDB).

A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or drift of atomic, molecular, and/or ionic species. The average of multiple stochastic simulations is used to qualitatively explain the measured BTI and SILC data. The difference in BTI and SILC time kinetics, variation in SILC time kinetics across reports, and oxide thickness dependence of TDDB Weibull slope variation are also qualitatively explained.

This study presents the reliability of diamond-like carbon (DLC) ultrathin films fabricated by DC magnetron sputtering as the gate dielectric layer in metal–insulator–semiconductor (MIS) devices. Stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) measurements were performed to determine the reliability of the devices. The MIS device with DLC film deposited at 1100-V bias exhibited little variation of SILC under different constant voltage stress times and had a long TDDB lifetime. The results indicate excellent reliability of DLC films used as gate dielectrics. Moreover, several soft breakdown events occurred during TDDB measuring. An extended percolation model was adopted for explanation of the current versus time characteristics.

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

Gate oxide integrity (GOI) are the most important concern in automotive applications of SiC-metal-oxide-semiconductor field-effect transistors (MOSFETs). As well as for the so-called B-mode defect density reduction, the time-dependent dielectric breakdown (TDDB) mechanism including the B-mode should be clarified in comparison to Si-MOSFETs. We have reported an anomalous behavior in the form of a continuous increase in the gate current during a Fowler-Nordheim stress test of commercially available SiC-MOSFETs, which we attributed to hole trapping near the SiO2/SiC interface. In this paper, the impact of this phenomenon on the TDDB lifetime is investigated, and the effects of AC on the TDDB lifetime enhancement in SiC-MOSFET under gate-switching operations (1 kHz and 100 kHz, at room temperature) are reported.

A systematic post-deposition annealing study on Silicon Carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) using atomic layer deposition (ALD)-deposited silicon dioxide (SiO2) layers was carried out. Anneals were done in oxidising (N2O), inert (Ar) and reducing (H2:N2) ambients at elevated temperatures from 900°C to 1300°C for 1 hour. Electrical characterisation results show that the forming gas treatment at 1100°C reduces the flatband voltage to 0.23 V from 10 V for as-deposited SiO2 layers. The density of interface traps (DIT) was also reduced by one order of magnitude to 2×1011 cm-2 eV-1 at EC-ET = 0.2 eV. As an indicator of the improvement, characterisation by x-ray photoelectron spectroscopy (XPS) showed that silicon enrichment present in as-deposited layers was largely reduced by the forming gas anneal, improving the stoichiometry. Time-dependent dielectric breakdown (TDDB) results showed that the majority of forming gas annealed samples broke down at breakdown fields of 12.5 MV × cm-1, which is about 2.5 MV × cm-1 higher than for thermally oxidised samples.

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

The impact of electrical stress on the defect generation behaviors in thin GeO2/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO2/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence ( ${Q} _{{\text {inj}}}$ ), and the fix charge generation is attributed to both ${Q} _{{\text {inj}}}$ and GeO2 thickness.

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density ( ${D}_{\textit {it}}$ ) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO.

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication.

A novel “atomic layer substrate biasing (ALSB)” technique is proposed to improve the dielectric properties including film density, dielectric constant (K), and leakage current density (Jg) and the reliability of nanoscale thin films. In the ALSB process, in situ Ar plasma generated by substrate biasing is layer-by-layer introduced into each cycle of atomic layer deposition. Energy delivery from the plasma toward the as-deposited layer boosts the migration of adatoms, leading to ∼10% increase of the film density, ∼3-order-of-magnitude reduction of Jg, and an increment of K being as large as 40.7 of a ZrO2 layer of ∼5 nm. The reliability enhancement upon the ALSB treatment is demonstrated by constant-voltage-stress (CVS) and the time-dependent-dielectric-breakdown (TDDB) tests, which confirm the suppression of stress-induced traps and a high electric field of 4.7 MV cm−1 projected for a 10 year lifetime. Significant improvements in the film density, Jg, K, and the reliability indicate that ALSB is a highly effective technique to modify the quality of ALD-deposited thin films, which can be widely used in a variety of fields including energy saving, green energy, nanoelectronics, and biomedical applications.

Time-dependent dielectric breakdown (TDDB) has become an important cause of failure for inter-metal dielectrics (IMD) in integrated circuits as feature sizes continue to shrink and novel materials are introduced. Although many studies have been conducted to understand the underlying physics of this issue, not enough work has been focused on evaluating TDDB lifetime of practical chip designs in the physical design stage. This paper proposes a full-chip TDDB failure analysis methodology to evaluate lifetime and identify TDDB hotspots in VLSI layouts, which are essentially interconnect wires that have high failure risk due to TDDB. The proposed method features three new techniques compared to existing methods. First, we have developed a partitioning-based scheme to deal with scaling of full-chip analysis by partitioning the full chip layout into small tiles. Second, for each tile, the new method calculates a newly-introduced TDDB failure metric called TDDB Damage for vulnerable wires. Such a wire-oriented TDDB analysis is the first of its kind and is very amenable for physical design as the wires can be easily adjusted or re-routed for TDDB-aware optimization. Third, the new method considers the impact of the non-uniform electric field calculated using the finite element method (FEM), which significantly improves the accuracy of TDDB risk evaluation. Experimental results show that the proposed new TDDB analysis method is more accurate than a recently proposed full-chip TDDB analysis method in which electrical field is treated as a constant value. Additionally, the proposed method can analyze a practical VLSI layout in a few hours.

In this article, we report the reliability characterization of 7-nm technology, in which the highly scaled sixth generation of FinFETs and 256-Mb static random access memory (SRAM) cells were newly developed by featuring extreme ultraviolet (EUV). The intrinsic reliability mechanisms of 7-nm FinFET including hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric-breakdown (TDDB) are similar to that of the previous nodes, and would not be degraded by introducing the scaled FinFET. Moreover, we found that the use of EUV single patterning of middle of line (MOL) and back end of line (BEOL) improves reliability distribution remarkably as compared to the previous nodes using argon fluoride (ArF) multiple patterning techniques. We successfully demonstrated SRAM and logic high-temperature operating life (HTOL) up to 500 h, indicating the robustness of product-level reliability. These findings strongly suggest that the 7-nm technology featuring EUV is fully ready for high-volume manufacturing as well as providing a near future logic production with high-quality reliability.

In this paper, two TDDB test structures of TSV, including Single-TSV and Dual-TSV, have been designed. In order to compare the availability between these two test structures, the electric field simulation and TDDB failure analysis have been carried out. The simulation results show that the Single- TSV is more prone to abnormal breakdown for its higher electric field between surface pads during TDDB test. On the contrary, the Dual- Tsvhas a greater probability of breakdown in the dielectric liner of TSV, because the maximum of electric field is located at the dielectric liner. The conclusion of TDDB failure analysis support the point of simulation. The Dual- Tsvhas better availability than the Single- TSV for the TDDB test of TSV. Furthermore, we discussed the guidelines for the design of TSV TDDB test structures.

Limiting the minimum spacing design rule of intra-metal lines and skipping the inter-metal layer in interconnects for more oxide spacing in order to improve TDDB margin for HV applications is not viable as it severely compromises the competitiveness of chip design. We demonstrated that with stringent control of the variation in oxide spacing between inter-metal layers, it is possible to improve TDDB margin for HV applications up to 12V for the specific low-k interconnects integration process. This technique provides a solution for cost saving without compromising reliability aspect.

This paper describes an advanced 5nm node back-end-of-line (BEOL) process integration based on an extreme ultraviolet (EUV) lithography process, atomic layer deposition (ALD) barrier metal (BM) and Cu reflow process. The ALD BM technology was integrated into Low-k in the damascene metallization. This advanced BEOL integration showed a good RC (resistance-capacitance) performance within +3% and an excellent 46% reduction in the via resistance compared to the physical vapor deposition (PVD) BM, and satisfied the reliability requirement for the time-dependent dielectric breakdown (TDDB) and the electro-migration (EM). Finally, ALD BM and Cu reflow process were developed for the advanced 5nm node BEOL integration, and the new process is implemented in order to achieve low via resistance and better device performance.

In this paper, we report the property and reliability of CuAl 2 and its effects of compositional shift within ±5%. Resistivity was found to be 7–8 μΩ· cm after annealing at 400 °C, even with compositional shift. Capacitance–Voltage (C–V) after Bias Thermal Stress (BTS) test showed no shift of flat–band voltage under the condition of 3.0 MV/cm × 30 min at 250 °C. Time–Dependent–Dielectric–Breakdown (TDDB) evaluation showed that the reliability is better than that of conventional Cu/TaN interconnects.

We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO 2 , LK3.0, SiCO and Si 3 N 4 films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO 2 , LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si 3 N 4 films.

Interposer to interconnect between the electronic components has been developed for the last few decades because it can improve the system performance effectively, compared to the system with intra-chip wiring. In this paper, the integrated stack capacitor (ISC) embedded interposer system was demonstrated with the approximately 8 times higher capacitance (C i ) than interposer with MIM (Metal / Insulator / Metal capacitor). The resistance and leakage current were measured and the results indicate that there were no the open fail inside the system. In addition, WLR (Wafer Level Reliability) was proved using TDDB (Time Dependent Dielectric Breakdown), Vramp, HTS (High Temperature Storage), TC (Thermal Cycle) and Pre-con tests and finally, all requirements of WLR are satisfied.

In this paper, we will report the reliability characterization of advanced FinFET technology which is developed by utilizing EUV. The intrinsic device reliability including HCI, BTI, and TDDB is comparable across FinFET technologies, and would not be degraded by scaling down. The use of EUV single patterning significantly improves reliability variation so that improved reliability lifetime compared to the use of ArF multi-patterning. Also, the fact that long-term reliability results support lifetime projection of TDDB follows power model, enables us to utilize more reliability margins in the scaled FinFET technologies.

We report the recent results of NiAl and CuAl 2 intermetallic compounds for advanced-node interconnect materials in place of Cu. Reported results of Co and Ru are briefly reviewed for comparison. CuAl 2 can be a good choice in terms of liner-free and barrier-free interconnections having a low resistivity and a good TDDB and EM reliability.

We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30A down to 10A. We demonstrate that while reducing Co liner thickness significantly reduces RC delay, there is a significant reduction in electromigration reliability below a thickness of 20A if used in conjunction with a PVD (physical vapor deposition) TaN barrier. However, if the PVD treatment is followed by deposition of a thin ALD (atomic layer deposition) TaN, the Co layer thickness can be scaled down to 10A without any penalty in either electromigration or time dependent dielectric breakdown (TDDB.) The combined PVD/ALD process with 10A Co enables a 14% reduction in RC delay relative to our control split.

In this study, the effect of microwave annealing (MWA), which has been attracting considerable attention as a low-thermal-budget method, on the high-k materials required for next-generation ultrahigh-integration semiconductor devices is investigated. Metal-oxide-semiconductor (MOS) capacitor-structure devices are fabricated using HfO₂ films, which are typical high-k materials; post deposition annealing (PDA) is then performed by MWA and compared to conventional thermal annealing (CTA). The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the fabricated HfO₂ MOS capacitors are measured to evaluate the leakage current, time-zero dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB), and frequency dispersion. Compared to the as-deposited state, the PDA-treated HfO₂ dielectric film is found to have reduced trap density, improved dielectric breakdown, frequency dispersion, and lifetime. In particular, the high-k HfO₂ thin films treated with MWA exhibit excellent surface properties, including a low root-mean square roughness (Rq) of 0.141 nm, thickness of 49.3 nm, and low inter face trap density (Dit) of 7.82 × 1012 cm-2eV-1 and electrical properties such as a high breakdown electric field (EBD) of 10 MV/cm, and high breakdown to charge (QBD) of 1,000 C/cm². As a result, the MWA-treated high-k HfO₂ thin films are smoother and denser than the CTA-treated thin films, and show better electrical properties and reliability, suggesting that the defects at Si the interface as well as in the high-k films are effectively removed.

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

The degradation behavior of Ag/SiO2-based conductive bridging RAM (CBRAM) is analyzed by conventional and expanded time-dependent dielectric breakdown (TDDB) models. By comparing the total cycling stress with time-to-breakdown ( ${t}_{\text {bd}}$ ) of the SiO2 used as a solid-electrolyte switching layer, it is clarified that the cycling stress does not reach the level at which dielectric breakdown of the SiO2 is triggered. On the other hand, we found that the ${t}_{\text {bd}}$ distribution after several cycles of set/reset stress agrees well with the simulated ${t}_{\text {bd}}$ distribution derived from expanded TDDB models, in which we assumed that a large amount of defects exists locally in the device area. This approach is useful for understanding the degradation in solid-electrolyte oxide of CBRAM.

Reduction of electrical resistance of middle-of-line (MOL) is now a primary requirement for advanced CMOS. In this paper, we demonstrate that the cluster-preforming-deposited (CPD) WSin (n ≤ 12) film is a promising contact material for S/D in CMOS; insertion of the WSin film reduces the electron SBH to 0.32 eV at W/n-Si and to 0.43 eV at Co/n-Si junctions. This SBH reduction is due to the fact that the WSin film has a low work function of 4.0 eV and effectively passivates the Si surface without forming an appreciable density of interface states, thereby releasing the Fermi level pinning at the Si surface. These junctions have an excellent stability against annealing up to 700˚C for W/WSin/n-Si and to 500˚C for Co/WSin/n-Si. Furthermore, this film significantly prevents the Cu diffusion with a TDDB barrier height of 1.33 eV under a 5 MV/ cm stress.

This paper discusses the design methodology of a voltage and temperature-sensitive ring oscillator (VT_RO), whose frequency has a similar dependence on voltages and temperatures as that of worn-out stress strength of a gate time-dependent dielectric breakdown (gate-TDDB). The VT_RO is used to monitor the accumulated environmental stress of gate-TDDB in reliability-oriented products, such as automotive microcontroller units. Therein, the VT_RO drives the on-chip stress counters during the product operations over the years. Three types of VT_ROs have been designed and compared, which have been fabricated by using 28 nm HKMG test chips; multi- ${V}_{{th}}$ VT_RO, single- ${V}_{{th}}$ VT_RO; and combinational use of both a voltage-sensitive ring oscillator and a temperature-sensitive ring oscillator. The measured frequencies of the three types of ring oscillators are in good agreement with the target model of power-law V dependency along with an exponential inverse ${T}$ dependency. The single- ${V}_{{th}}$ VT_RO seems most promising in terms of product applicability, design difficulty, and low power.

Mechanisms of time-dependent dielectric breakdown (TDDB) in nonfilamentary a-Si/TiO2 RRAM cell [a-vacancy modulated conductive oxide (VMCO)] have been examined in this paper, including defects generation in the grain boundary, defects clustering, and different defects generation rates in a-Si and TiO2 layers. The unique feature of a bimodal Weibull distribution at low-resistance state (LRS) and a single shallow slope distribution at high-resistance state (HRS) cannot be explained by the above mechanisms. By using a combination of constant voltage stress, time-to-breakdown Weibull distribution, and random telegraph noise (RTN)-based defect profiling in devices of various sizes, layer thicknesses, and processes, it is revealed that the defect profile is modulated when switching between HRS and LRS and the correlation of defect profile modulation with local defect generation rate can explain the difference in Weibull distributions at HRS and LRS. The transition from bimodal distribution at LRS to a single-steep slope with thinner a-Si layer, and the good area scaling of Weibull distribution at HRS but not at LRS, can also be explained. The critical layers affecting the TDDB in a-VMCO are identified, providing useful guidance for device performance improvement.

Non-destructive electrical characterization was performed to detect copper migration in a degraded through-silicon via structure after various stressing conditions, such as elevated temperature exposure, temperature cycling, and electrical biasing. They were performed either independently or as a combination with electrical bias for comparison. Variations in the electrical characteristics reflect the presence of copper. The electrical characteristics were also able to monitor the transport of copper ions from an applied electric field. Physical failure analysis was performed to verify the presence of migrated copper, correlating with the changes observed during electrical measurement. With this understanding, reliability assessments become possible where this paper seeks to value add to verify the influence of Cu migration on the conduction mechanism and time-dependent dielectric breakdown (TDDB) lifetime, in which there is currently a lack in understanding. The conduction mechanism was fitted with experimental data before and after degradation and it was deduced that the Poole–Frenkel conduction mechanism is the dominant mechanism after degradation. However, this is dependent on the copper oxidation state which was verified to change over time from Cu2O to CuO by X-ray photoelectron spectroscopy. TDDB experiments were also performed based on this understanding and found that the presence of copper may accelerate or decelerate time to failure. TDDB lifetime was fitted experimentally and is found to be in good agreement with the $\sqrt {E} $ model. It was verified experimentally by measuring the time to failure at low ${E}$ -field within reasonable failure time, rather than extrapolating from data at high field.

In this paper the gate oxide reliability of SiC MOSFETs has been tested under different stress conditions. Discrete devices of the 1.2 kV class with planar and trench MOS-structure have been examined under positive and negative stair-shaped increased gate bias until the time dependent dielectric breakdown (TDDB). This test procedure was developed to expose extrinsic failures in high temperature gate bias tests. Additionally, three prototype power modules equipped with 6.5 kV SiC MOSFETs have been tested under positive, negative constant voltage gate bias and positive stair-shaped increased gate bias. The threshold voltage together with the output characteristic has been recorded before test start and after every stress period. A significant impact from the V GS(Th) -drift on the output characteristic is shown. Hence, it is recommended to consider the TDDB and the V GS(Th) -drift for lifetime predictions.

SiC power electronics offers several advantages over Si-based technologies in terms of low-loss switching and power conversion efficiency. Especially 1.2kV SiC power MOSFETs are promising candidates to replace Si IGBTs in various applications. However, the SiC/dielectric interface exhibits peculiarities and challenges that prevent the exploitation of the full potential of these devices. This contribution is dedicated to the Time Dependent Dielectric Breakdown (TDDB) of high-k/SiC interfaces as well as to the threshold voltage (V TH ) hysteresis effects under harsh repetitive switching conditions of 1.2kV high-k SiC power MOSFETs, particularly using large negative gate voltage never studied before.

The failure mechanism of drain bias TDDB for HV De-PMOS was studied, which is induced by minority, electrons for PMOS, from ion impact ionization at high V d injection to drift region dielectrics. Multistage Ig-t curve behavior was observed during off-sate drain bias TDDB test, electrons injected into drift region (Ig increase) at initial stage, electrons trapped in drift region dielectrics (Ig decrease) at 2nd stage and percolation path formed (gate oxide breakdown) at last stage. Furthermore, power law model, used to extrapolated drain bias TDDB lifetime, and its characteristics, n value, Ea, width factor were studied. Finally, through quick method to screen effective result from various optimized process experiments, drain bias TDDB lifetime was significantly improved.

Reliability test efficiency and accuracy are both important to technology development. In this study, we develop a new gate oxide reliability test method, called tunable ramp voltage stress (TRVS). It can perform a quick gate oxide reliability test like breakdown voltage (VBD) though a ramp voltage stress (RVS) method, and also receive the data accuracy similar to conventional TDDB, which is a constant voltage stress (CVS) method. Moreover, we exploit this method to enable large-sample-size measurement. More samples imply lower projection error. This greatly benefits TDDB lifetime projection of devices for automotive applications.

Moisture diffusion behavior in an ultra-low-k (ULK) dielectric has been studied using a ring oscillator. The diffusion constant of water in the ULK dielectric was found to be temperature and moisture concentration dependent and can be modeled as an Arrhenius function with an activation energy of 0.27 eV. Furthermore, the impact of moisture on dielectric reliability was investigated by a comb-meander test structure without edge seals. The experimental results showed that moisture could easily be absorbed by an ULK dielectric. The absorbed moisture cannot be completely desorbed with high temperature dry baking. The presence of moisture has significant impact on the dielectric breakdown voltage and the time-dependent dielectric breakdown (TDDB) lifetime.

We evaluate the reliability of a semidamascene BEOL scheme with direct metal etched (DME) Ruthenium and 16 nm wide air gaps (AG). First, we show that Ru can be barrierless independent of the type of deposition (ALD, CVD, PVD) using planar capacitor structures with a metal-etch-based flow. We present TDDB results of semidamascene Ru +AG showing V max to be above 1.5 V for TTF 0.1% of 3 km long lines at 100°C (using power law model). We show no change in resistance after >1200 h during electromigration tests at 330°C with 5 MA/cm2 stress. We identify increased Joule heating as a reliability concern.

In this work, we studied the behavior of gate oxide (GOx) breakdown of 1200V 4H-SiC DMOSFETs by a screening process of voltage ramp (vramp). By employing vramp between 40-50V on a 50nm GOx, early failures below 50V, which could be infant or extrinsic failures in time-dependent-dielectric-breakdown (TDDB) testing, were screened out. In addition, the results indicate that early failures correlate to the density of large pit defects on epi-wafer as well as to gate area of the devices, which have implications on the epi quality required for MOSFETs and for achievable yield on large-area SiC MOSFETs screened for long-term gate reliability. We also identified an electric field limit on the screening voltage, above which the traditional upward drift of threshold voltage (V Th ) due to positive gate bias transitions to a downward drift, which can seriously degrade device performance.

Time dependent dielectric breakdown (TDDB) reliability is studied on interfacial layer (IL)/high-K gate stack of Gate-All-Around Nanosheet (GAA-NS) N- and P-type Field Effect Transistors (FETs) with volume-less multiple threshold voltage (multi-Vt) integration scheme enabled by the dual dipoles (n-dipole and p-dipole). We report for the first time Key TDDB Modeling parameters: voltage acceleration exponent (VAE), Weibull slope ( $\beta$ ), and activation energy (E a ) and show robust TDDB reliability in multi-Vt NS transistors enabled by different dipoles.

Time dependent dielectric breakdown (TDDB) of various device architectures was found to depend on bias polarity that modulates local electric fields enhanced by interface roughness. If the electrode with interface roughness is biased into accumulation, it consistently results in a higher acceleration parameter $(\gamma)$ and in most cases a smaller Weibull slope $(\beta)$ of the E-model. This introduces error to the projected dielectric lifetime. Two-dimensional (2D) simulations were conducted to evaluate the peak electric field under various degrees of interface roughness and several applied voltages. The results show that the distribution of the peak electric field widens as the field strength increases. This offers a qualitative insight into the observed trend of $\gamma$ and $\beta$ according to the biasing conditions.

Fluorine (F) implantation into gate poly-Si was used to incorporate F atoms in gate oxide films. Different F profiles in depth direction of gate oxide films were prepared. Enhanced segregation of F atoms at SiO2/Si interfaces was important for improvement of time dependent dielectric breakdown (TDDB) lifetime and suppression of hot carrier degradation. TDDB and low frequency noise dependences on gate length suggested that F profiles in lateral direction of gate oxide films should be cared for reliability of short channel devices.