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Event-driven processor networks have been proposed as an effective way of exploiting recent advances in field-programmable technology. This paper explores an approach to enhancing the performance of event-driven processor networks for specific applications: attaching to the processor network accelerators with custom-designed logic. We present a design flow of this approach, and apply the flow to a heatplate application.

This paper provides a novel compilation approach that addresses the complexity of mapping high-level descriptions to heterogeneous platforms, improving design productivity and maintainability. Our approach is based on a co-design methodology decoupling functional concerns from optimisation concerns, allowing two separate descriptions to be independently maintained by two types of programmers: application experts focus on algorithmic behaviour, while platform experts focus on the mapping process. Our approach supports two key requirements: (1) Customisable optimisations to rapidly capture a wide range of mapping strategies, and (2) Reusable strategies to allow optimisations to be described once and applied to multiple applications. To evaluate our approach, we develop Artisan, a meta-programming tool for codifying optimisation strategies using a high-level general-purpose programming language (Python 3), offering full design-flow orchestration of key components (source-code, third-party tools, and platforms). We evaluate Artisan using three case study applications and three reusable optimisation strategies, achieving at least 24 times speedup for each application on CPU and FPGA targets with little application developer effort.

Supporting a high level of parallelism for statistical algorithms on FPGAs is often hindered by the uncertainty of random memory access and the associated difficulty of scheduling at runtime. By exploiting the statistical properties to tolerate memory request reordering and droppage, speed enhancement and resource reduction of the design can be optimized, leading to a more efficient and parallelizable design. This paper introduces a novel lossy multiport memory capable of high memory bandwidth, providing concurrent accesses to a single address space through multiple ports. The proposed architecture contains parallel memory banks connected by lossy switch networks to multiple input ports and local ring buffers. For 4 parallel read/write ports, our design reduces BRAM usage by 68% while having the operating frequency increased by 50% as compared to state-of-the-art memory designs. The drop rate of the design is 2% under full port utilization, and is reducible without altering the architecture at runtime. With a simple and scalable structure, this memory architecture can be scaled up to 64 parallel read/write ports and beyond, which outperforms most of the existing designs. Experiments show that this lossy memory can reduce slice usage by 90.8 times for random forest training and data compression, with a reduction in accuracy of only 2%.

We present an approach to enable run-time, in-circuit assertions and exceptions in reconfigurable hardware designs. Static, compile-time checking, including formal verification, can catch many errors before a reconfigurable design is implemented. However, many other errors cannot be caught by static approaches, including those due to run-time data. Our approach allows users to add run-time assertions and exceptions to a design, giving multiple ways to handle run-time errors. We also allow imprecise assertions and exceptions, so that the origin of a failed assertion or raised exception is blurred. Users can take advantage of exception imprecision to trade performance for accurate location of errors. Our work includes a high-level approach to adding assertions and exceptions to a design, a concrete implementation for Maxeler streaming designs, and an evaluation. Results show low overhead for supporting assertions and exceptions in hardware design targeting FPGAs. For example, the cost of including assertions lies between 5% in lookup tables and 15% in Block RAMs in addition to the area used by the original design, due to logic used to implement assertion conditions, and buffers used to store assertion results. Furthermore, imprecision gives immediate benefits and up to 48% speedup over precise exceptions.

Commonly used in software design, assertions are statements placed into a design to ensure that its behavior matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new hardware design language-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-and-routed circuit without affecting the existing design. We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to this paper is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. We use network-flow techniques to route necessary signals to assertions via spare flip-flops, eliminating any performance degradation, even on large designs (92% of slices in one test). Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above 200 MHz, at the cost of a small power penalty.

© 2016 IEEE. To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.

Summarization: The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis. Presented on: Microprocessors and Microsystems