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We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of $7.9 \times 10^{\mathrm {\mathbf {7}}}$ and $4.2 \times 10^{\mathrm {\mathbf {7}}}$ , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of −2.3–1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.

By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio ( $\sim 10^{10}$ ), steep sub-threshold swing ( $66\sim 108$ mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.

In this letter, we demonstrate 0.6- $\mu \text{m}$ ZnON thin-film transistors (TFTs) with the field-effect mobility of 71 cm $^{\mathrm {\mathbf {2}}}$ /V-sec, which to the best of our knowledge is the highest value ever reported on submicrometer oxide–semiconductor TFTs. The drive current, field-effect mobility, and subthreshold slope of ZnON TFTs are significantly improved as compared with their counterpart ZnO TFTs of the same channel dimensions and structure. Such an improvement in the field-effect mobility primarily results from a considerable reduction in the series source/drain (S/D) resistances because of suppression in an interfacial layer formation between Al S/D pads and the channel layer.

In this paper, high-performance InGaZnO (IGZO) thin-film transistors were fabricated with film-profile-engineering scheme. The impacts of gate dielectric, O 2 /Ar ratio during the sputtering of the IGZO, and annealing ambient on the device performance were investigated. It is found that the turn-ON voltage of the device is closely related to the gate dielectric material. For the devices with Al 2 O 3 as the gate dielectric, decent performance in terms of high ON/OFF current ratio (>10 8 ), extremely steep subthreshold swing (62 mV/decade), and good mobility (19.8 cm 2 /V·s) is obtained. The influences of O 2 /Ar flow ratio are distinct for the devices with Al 2 O 3 gate oxide. Significant improvement in the stability of the devices to the environment is achieved with the anneal done in a low-pressure N 2 ambient.

A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrier-lowing value (100 mV/V).

100-nm indium–gallium–zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal ${\rm Al}_{2}{\rm O}_{3}$ gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio $({>}10^{7})$ and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.

A novel approach, which can delicately form a desirable film profile for deposited gate oxide, channel, and source/drain contacts of oxide-based thin-film transistors (TFTs) is proposed. To demonstrate the film-profile engineering concept used in this approach, a simple one-mask process was developed for fabricating ZnO TFTs with submicrometer channel length. The fabrication takes advantage of a suspended bridge hanging across the device to tailor the desirable profile of deposited films with proper tools. The fabricated devices show high ON/OFF current ratio (>109), steep subthreshold swing (71-187 mV/decade), and high mobility (21-45 cm2/V·s). Very small variation in device characteristics among the devices with the same channel dimensions is also confirmed.

$p$ -type SnO thin-film transistors (TFTs) using a nominally symmetrical double-gated (DG) structure were studied in this letter. The top and bottom gates can be biased independently (single-gated mode) or jointly to switch the device (DG mode). For the latter operation, it is shown that ON current, subthreshold swing, and OFF-state current of the SnO TFT are all improved as compared with the operations when only one of the two gates is biased. As the device is operated under the DG mode, field-effect mobility of 6.54 cm2/V-s, high ON/OFF current ratio of $> 10^{5}$ , and subthreshold swing of 143 mV/decade are obtained. Moreover, the capability of the device in tuning its transfer characteristics under the single-gated operation with the bias applied to the opposite gate is also confirmed.

Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.

We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.

In this work, we study the electrical characteristics of planar poly-Si junctionless (JL) thin-film transistors (TFTs) with 10 nm-thick channel and various gate width. The output current of JL devices is drastically larger than that of the control device with an undoped channel, owing to the abundant carriers contained in the channel of the JL devices which tends to reduce both channel and source/drain series resistances. Subthreshold swing of the JL devices is found to be larger than the control ones, owing to the existence of a depletion layer in the channel. Nonetheless, excellent on/off current ratio (>1E+07) is achieved, thanks to the use of the ultra-thin channel.

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 × 1019 cm-3 and the fixed charge density to be around -6 × 1012 cm-2. The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.

IGZO transistors with various gate/drain-offset lengths (L gdo ) were fabricated with the film-profile-engineering method. Breakdown voltage (VBD) of the fabricated devices increases while transconductance (gm) decreases with increasing L gdo . In contrast, threshold voltage and subthreshold swing remain relatively unchanged. V bd of ∼80 V is obtained with L gdo of 0.3 μm. Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.

Short-channel zinc oxynitride (ZnON) thin-film transistors (TFTs) were fabricated based on the film profile engineering in combination with e-beam lithographical patterning. ZnON films were deposited using reactive magnetron sputtering in N 2 /O 2 ambient and exhibit a Hall mobility of 95 cm2/V-s. A ZnON TFT with channel length of 147nm shows high on/off current ratio of 5×107 and field-effect mobility of 9.1 cm2/Vs, which are superior or comparable to their counterparts of IGZO or ZnO TFTs.

Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (G m ). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable Vth for high-gain BEOL logic gate inverters in a unique film-profile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4–0.8 μm) in a single step, leading to a wide-ranging tunability in Vth of −0.2–+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 μm IGZO TFT and 0.7μm IGZO drive-transistor, respectively, at operation voltage (Vdd) of 9V.

This work reports the first experimental submicron and sub-100 nm ZnON TFTs with excellent performance. Field-effect mobility values as high as 55 and 9.2 cm2/V-s were measured from ZnON TFTs with channel lengths of 0.5 μm and 75 nm, respectively. Those are the highest values ever reported on oxide-semiconductor TFTs of comparable channel length. The results confirm ZnON TFTs as an effective building block for the construction of BEOL circuits integrated in a chip.

In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices.

Poly-Si junctionless (JL) TFTs with various structural parameters were characterized. Owing to the presence of abundant carriers in the channel and elimination of junctions, dramatically increased current drive is achieved with the JL device. Improved control over short-channel effects and characteristics fluctuation is also achieved with a thinner gate oxide.

A new five-mask-count process for fabricating CMOS inverters with poly-Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well-designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.

This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.

Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.

In this study, dynamic hot carrier effect in the MILC p-channel TFT device has been characterized by the unique struture. This novel structure is capable of spatially resolving the hot carrier effect and is highly sensitive to detect the defect-rich region. The dynamic hot carrier stress has been focused on the impacts of the frequency, the rise time and the fall time. In varied frequency stress condition, the degradation in the drain-sided monitor transistor (DMT) increases monotonically with increasing frequency, infering that more defects are generated by extra dynamic stress contribution in the drain side and degrade the characteristic of device. Under varied fall time stress condition, the oncurrent degradtion is severe with decreasing fall time due to the extra voltage drop during voltage switch. The final part is effect of rise time. While device switches, the large voltage drop exists in the junction between the channel and the drain, which resulted in anothor hot carrier degradation.

In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, -shaped gated , and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.

A poly-Si nanowire (NW) thin-film transistor configured with the double-gated scheme was fabricated and characterized. The fabrication process features the clever use of selective plasma etching to form a rectangular NW underneath a hard mask. In this paper, we show that replacing the original ion-implanted poly-Si with in situ doped poly-Si for the source/drain significantly enhances the device performance, including steeper subthreshold swing (SS), larger on/off current ratio, and reduced series resistance. In particular, the SS is improved to a record-breaking low value of 73 mV/dec, which, to the best of our knowledge, is the most ideal ever reported for a poly-Si based device. The new NW transistors with such excellent switching properties are highly promising for reducing power consumption and operational voltage in practical circuit applications.

We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal–oxide-semiconductor field-effect transistors. Excellent device characteristics were verified.

A new method is proposed and demonstrated to fabricate planar thin-film transistors and trigated nanowire (NW) devices simultaneously on the same panel. By using an oxide-nitride-oxide stack as the gate dielectric, the NW devices could also serve as nonvolatile Si-oxide-nitride-oxide-Si (SONOS) memory devices. Our results indicate that the combination of trigate and NW channels help to improve the device performance in terms of steppers subthreshold swing and reduced threshold voltage. Improvement in programming and erasing efficiency of the nonvolatile SONOS memory devices is also demonstrated with the trigated NW structure.

This study examines the effects of plasma-induced damage (PID) both on advanced SiO 2 /poly-gate and Hf-based high- k /dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high- k /metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high- k /metal-gate CMOS technology.

In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventionalSiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

In this paper, we employed a new test structure to characterize the alternating-current (AC) hot-carrier (HC)-induced degradation in poly-Si thin-film transistors. High sensitivity in detecting the damage and the capability of directly resolving the damage location are demonstrated due to the unique feature of the test structure. Our results indicate that the major degradation is induced in the turn-off stages of the AC-stress signal when applied to the gate and in the turn-on stages of the AC-stress signal when applied to the drain. The availability and energy relaxation of channel HCs are considered to explain the experimental findings.

A simple and low-cost method to fabricate poly-silicon nanowire field effect transistor (poly-Si NW FET) for biosensing application was demonstrated. The poly-silicon nanowire (poly-Si NW) channel was fabricated by employing the poly-silicon (poly-Si) sidewall spacer technique, which approach was comparable with current commercial semiconductor process and forsaken expensive E-beam lithography tools. The electronic properties of the poly-Si NW FET in aqueous solution were found to be similar to those of single-crystal silicon nanowire field effect transistors reported in the literature. A model biotin and avidin/streptavidin sensing system was used to demonstrate the biosensing capacity of poly-Si NW FET. The changes of I(D)-V(G) curves were consistent with an n-type FET affected by a nearby negatively (streptavidin) and positively (avidin) charged molecules, respectively. Specific electric changes were observed for streptavidin and avidin sensing when nanowire surface of poly-Si NW FET was modified with biotin and streptavidin at sub pM to nM range could be distinguished. With its excellent electric properties and the potential for mass commercial production, poly-Si NW FET can be a very useful transducer for a variety of biosensing applications.

Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 108. These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.

In this study, the effects of Si3N4 layer capping and TEOS buffer layer inserted prior to the Si3N4 deposition on the NMOS device characteristics as well as correlated hot-electron degradations were investigated. The devices were built on two kinds of the substrates, namely, Cz and hydrogen-annealed (Hi) wafers. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. By exerting the accelerated stress test, we could study the hot-electron degradation thoroughly in terms of threshold voltage shift (ΔVTH), transconductance degradation (ΔGm) and so on. The TEOS buffer layer could effectively block the diffusion of hydrogen species from the Si3N4 capping layer into the channel and the Si/SiO2 interface during the Si3N4 deposition as well as subsequent thermal cycles.

Although the incorporation of a SiN capping layer could dramatically enhance device performance, the accompanying hydrogen species contained in the capping layer may aggravate hot-carrier reliability. In order to alleviate this shortcoming, we vary the precursor flow conditions and deposition temperature of SiN film during plasma-enhanced chemical vapor deposition (PECVD) and study their impacts on the device performance and reliability. We found that SiN film with higher nitrogen content depicts larger tensile stress and therefore better mobility. More importantly, the resistance to hot-carrier degradation is also improved by increasing N2 gas flow rate and deposition temperature because of less hydrogen diffusion from the capping layer.

For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -VG stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.