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High aspect ratio (HAR) silicon nitride and silicon oxide (ONON) channel hole patterning in 3D NAND flash presents great challenges. This report summarizes some of the recent progress in patterning from the perspective of HAR etching and deposition-etch co-optimization (DECO). HAR etching mechanisms will be discussed, with a focus on how to reduce the aspect ratio-dependent etching (ARDE) effect. Highlights of the new low-temperature etch process will be presented, with significant improvement in the ARDE being observed. New simulation results from a Monte Carlo feature-scale model provide insights into ion scattering and mask interactions on the control of the channel hole profile. DECO is a new frontier to enable better control of the channel hole shape at HAR. Film tier optimization and carbon liner insertion results show improvement in channel hole profile control.

This paper studies the transport of neutral etch species in cylindrical holes, which are of interest for advanced memory devices. The etching of these devices utilizes ions and neutral reactive species, which must travel to the etch front deep inside the feature. For gas pressures in the millitorr and feature sizes in the nanometer range, neutrals reach the bottom of an etching feature via the Knudsen transport1,2. For an aspect ratio of depth to diameter of 100:1, the flux at the bottom of the feature is only 1.3% of the incoming flux. This is a challenge for etching of advanced memory devices with ever increasing aspect ratios. We present computational results for the neutral transport in high aspect ratio features as a function of aspect ratio, profile shape, and surface processes such as adsorption, desorption, and diffusion of neutral species. Pertinent parameters are varied over a wide range to identify salient trends. When available, we include values for the case of fluorine radicals on silicon and silicon oxide in the parameter scans. The results predict that steady state transmission probability increases meaningfully in the presence of surface diffusion. Spontaneous and collision induced desorption of adsorbed neutrals on their own does not change steady state transmission probability, but they affect the time to reach it. In the presence of surface diffusion, however, spontaneous desorption increases the transmission probability, while desorption due to collisions with co-flowing nonreactive gas reduces it. These results indicate an enhancement of neutral transport at low surface temperatures that facilitate physisorption and surface diffusion.

In this article, we give an overview about the chemical and physical processes that play a role in etching at lower wafer temperatures. Conventionally, plasma etching processes rely on the formation of radicals, which readily chemisorb at the surface. Molecules adsorb via physisorption at low temperatures, but they lack enough energy to overcome the energy barrier for a chemical reaction. The density of radicals in a typical plasma used in semiconductor manufacturing is one to two orders of magnitude lower than the concentration of the neutrals. Physisorption of neutrals at low temperatures, therefore, increases the neutral concentration on the surface meaningfully and contributes to etching if they are chemically activated. The transport of neutrals in high aspect ratio features is enhanced at low temperatures because physisorbed species are mobile. The temperature window of low temperature etching is bracketed at the low end by condensation including capillary effects and diminished physisorption at the high end. The useful temperature window is chemistry dependent. Besides illuminating the fundamental effects, which make low temperature processing unique, this article illustrates its utility for semiconductor etching applications.

Thermal atomic layer etching is rapidly becoming an important complementary processing technology in the manufacturing of 5 and 3 nm devices in the semiconductor industry. Critically, architectures such as 3D NAND and 3D DRAM require conformal isotropic etching to remove material such as HfO2 in hard-to-reach locations with aspect ratios that can be greater than 50:1. To achieve repeatable device performance throughout a 3D stack, the removal rate (etch per cycle) of the etched material during an etch process needs to be controlled such that the overall etch amount is the same from top to bottom of the device stack. In this work, the reaction kinetics of reactants and byproducts during a cyclical ligand exchange-based atomic layer etching (ALE) process have been modelled. This ALE process consists of two steps: a fluorination step followed by a fluorine-to-chlorine ligand exchange-based removal step. Modeling was performed for each of those steps separately. Experimental data revealed that the fluorine dosing during the fluorination step was predominantly responsible for controlling the etch rate of the ALE process but had only a minimal impact on the etch profile inside high aspect ratio holes. The ligand exchange dosing, on the other hand, predominantly controlled the etch profile (depth loading) with equal etch rates from top-to-bottom, obtained when the step was operated close to saturation. The model predicts that the chemical reaction rate of dimethylaluminum chloride (DMAC) on a fluorinated surface during the ligand exchange step is 9.1 s−1, about 46 times greater than the reaction rate of hydrogen fluoride (HF) on the hafnium oxide surface during the fluorination step (only 0.2 s−1). Furthermore, modeling results revealed that the sticking coefficient for DMAC on a hafnium fluoride surface far exceeded that of HF on a hafnium oxide surface in the conditions modelled (0.94 s−1 for DMAC vs 0.0058 s−1 for HF). With these modeling results, the different roles fluorination and ligand exchange steps have regarding the control of etch rate per cycle and profile inside high aspect ratio holes can be explained.

Thermal atomic layer etching is rapidly becoming an important complementary processing technology in manufacturing 5 and 3 nm devices in the semiconductor industry. Critically, stacked chip architectures such as 3D NAND and 3D DRAM require conformal isotropic etching to remove material such as HfO2 in hard-to-reach locations with aspect ratios that can be >50. To achieve repeatable device performance throughout a 3D stack, the removal rate (etch per cycle) of the etched material during an etch process need to be controlled such that the overall etch is the same from top to bottom of the device stack. In this work, we have modelled the reaction kinetics and transport processes of reactants and by-products during a cyclical ligand exchange-based ALE process. This ALE process consists of two steps: a fluorination step, followed by a fluorine-to-chlorine ligand exchange-based removal step. Experimental data revealed that the fluorine dosing during the fluorination step was predominantly responsible for controlling the etch rate of the ALE process but had only a minimal impact on the etch profile inside these holes. The ligand exchange dosing, on the other hand, predominantly controlled the etch profile (depth loading) with equal etch rates top-to-bottom obtained when the step was operated close to saturation. Our model predicts, in agreement with the experiment, that adsorption and reaction rates during fluorination on HfO2 surfaces are significantly slower than transport times inside these deep holes leading to essentially flat fluorination profiles even if the fluorination step is not operated in saturation mode. In contrast, transport rates with the ligand exchange molecule are slow in comparison but adsorption and ligand exchange rates with the fluorinated hafnium appear to be significantly higher than for fluorine during the fluorination step. Slow transport in combination with high surface reaction rates for the ligand exchange step led to an etch rate that was dependent on aspect ratio (feature depth) in processes that used sub-saturation exposures.

Over the past decade, the demands for 3D NAND flash memory devices have been increased tremendously due to ever growing digital economics in consumer electronics, data centers, IOT, healthcare and automotive industries. The growth is further accelerated during the recent Covid period. The industry was able to keep up the scaling roadmap by stacking more memory cell in vertical direction to realize higher bit density at reducing cost per Gig-bit. Unlike devices scaling via feature size reduction, 3D NAND flash vertical stack scaling puts challenges mostly on film deposition and etch. Among many steps, high aspect ratio (HAR) ONON channel hole formation modules remained the most critical steps. Forming billions of perfect channel holes from top to bottom without distortion and twisting is the grand challenge. Besides individual etch and deposition module optimization, deposition and etch Co-optimization (DECO) could provide new opportunities. In this paper, we will present a summary of the recent progress in the approaches and the benefits of DECO as potential pathways to overcome the HAR ONON patterning. We will discuss the ONON Tier Optimization for profile control to reduce the top bowing and enlarge the bottom CD. We will introduce a sacrificial liner approach to prevent top CD enlargement at deeper etch depth. We will also discuss new mask materials for better etch selectivity and profile control to enable the scaling roadmap.

In the manufacturing of integrated circuits, etching and deposition processes with and without plasma are widely used. Except for physical processes such as Physical Vapor Deposition and Ion Beam Etching, these processes leverage the adsorption of reactive neutrals to enable chemical reactions at the wafer surface. In this paper, we will investigate the fundamentals and applicability of low temperatures to stimulate physisorption of neutrals. Among the points of interest for this approach are the use of less reactive gases, higher fluxes to the surface, new transport mechanisms into high aspect ratio features, and 3D effects thanks to condensation in small features. We will discuss temperature and pressure ranges for relevant material and pre-cursor gas combinations and means to initiate the deposition and etching reactions. An overview of experimental results from our research and the literature will be presented.

3D NAND flash scaling relies mainly on increasing vertical stack height, thus putting challenges mostly on film deposition and etch. Among various fabrication steps, high aspect ratio (HAR) ONON channel hole etch remains the most critical step. One unique aspect of the 3D NAND process flow is that nitride film in the ONON pair is a sacrificial layer that is been replaced with W at a later stage. The SiN removal process flow provides opportunities to look at possibilities of optimizing oxide and nitride films at different layers to enable better channel hole etch, such as enlarging bottom hole CD, reducing bowing and twisting in the middle area, and etc. In this paper, we will highlight the approaches and benefits on deposition and etch co-optimization as one potential pathway to overcome barrier in HAR ONON channel hole patterning. Besides ONON HAR, hard mask is another key focus. We will also discuss the possible mask material selection consideration based the overall film properties, etch selectivity and final clean/removability perspectives.

Dependence on ion beam energy, ion species, and incidence angles is investigated to reduce sidewall re-deposition on the magnetic tunnel junction barrier. Experimental and simulated etch data, for a representative spin-torque transfer random access memory structure with 40 nm critical dimension and 150 nm pitch, indicated a reduction in the sidewall re-deposition when operating at: high angle, high voltage, and with Xe as the source gas. The Monte Carlo binary collision model simulations showed re-deposition thickness reduced by ~75% with Xe versus Ar at 1 kV beam energy and 30° incidence angle.

Phase change materials (PCM) have emerged as the leading candidate for next generation non-volatile storage class memory as demonstrated by the commercialization of 3D Cross Point memory. More recently, PCM memories have been explored for non-von Neumann system architectures with potential applications in neuromorphic computing. To accelerate the widespread adoption of PCM technology, better understanding of the unit processes and its interactions is needed to cost effectively produce high fidelity PCM devices. Challenges in creating cross point PCM architectures are significantly different from more dominant technologies such as DRAM and 3DNAND. From a device perspective, the PCM composition is sensitive to crystallization temperature, which translates to potentially large changes in the switching resistance for small changes in composition. From a material perspective, phase change chalcogenides readily etch in various plasma etch chemistries with the many etch chemistries exhibiting bulk composition changes. Furthermore, slight changes in the PCM composition can be removed by wet clean. In this regard, one of the main process challenges is to not etch chalcogenides laterally in order to maximizing the device volume. Finally, from a structural perspective, PCM are relatively soft with Young’s modulus that can be 3x smaller than materials found in DRAM/3DNAND stacks (e.g. Si, SiOx). Soft chalcogenides can lead to increased line bending, especially when the chalcogenide is at the bottom of the stack. As a result, post wet clean pattern collapse and line bending from film stress can be challenging to manage. To meet the material and structural challenges, we developed an integrated system combining dry etch, wet clean, and deposition process modules. Comprehensive understanding of each process module as well as the interactions of different process modules has been obtained. We will present some holistic process solutions combining dry etch, wet clean, and deposition to deliver collapse free, high fidelity PCM structures.

Isotropic Atomic Layer Etching can be used to remove materials such as high-k oxides or certain metals from high aspect ratio (HAR) structures from sidewalls and even non-line-of-site locations where access via reactive ion etching would be challenging or impossible. Those locations could be sites below the shelves in 3D-NAND stacks or around wires in GAA structures. The etch rate per cycle of Thermal Isotropic ALE should in principle be insensitive to aspect ratio and line-of-sight accessibility if both reaction steps are fully saturated. Deviations from the ideal behavior have been reported previously for Al2O3 ALE with alternating HF and DMAC cycles [1]. Without mitigation, this behavior would ultimately lead to performance differences in devices located at the bottom of the structure compared to those at the top. In this work we present a method to counteract the unwanted depth dependence of the etch rate when etching HfO2 with the HF/DMAC ligand exchange ALE process. To mitigate the depth dependence, we explored the use of operating the ALE process at ultra-high pressures up to 5 Torr and over a wide temperature range. We found that under these conditions, the modification step has been boosted such that it takes place near its saturation regime so that top-to-bottom etch rate differences could be reduced. We show that high pressure and temperature mostly target the fluorine profile along a structure and removal step times needed to be allowed sufficient time to clear the entire modified layer. We give an example of such application in a 50:1 aspect ratio 3D NAND test structure.

This article reviews the state-of-the art status of thermal atomic layer etching of various materials such as metals, metal oxides, metal nitrides, semiconductors, and their oxides. We outline basic thermodynamic principles and reaction kinetics as they apply to these reactions and draw parallels to thermal etching. Furthermore, a list of all known publications is given organized by the material etched and correlated with the required reactant for each etch process. A model is introduced that describes why in the nonsaturation mode etch anisotropies may occur that can lead to unwanted performance variations in high aspect ratio semiconductor devices due to topological constraints imposed on the delivery of reactants and removal of reactant by-products.

In this work, the authors have investigated the dependence of the anisotropy level in an atomic layer etching (ALE) process of Al2O3 on form factor constraints when the ALE process involves etching in non-line-of-sight locations beneath a silicon nitride mask. In the experiments described here, thermal etching of Al2O3 without the use of any direction-inducing plasma components was explored utilizing the well characterized hydrogen fluoride/dimethyl-aluminum-chloride atomic layer etching process. The degree of anisotropy was quantified by measuring the ratio of lateral etch rate of this process in comparison to the vertical etch rate as a function of process step time inside 60 nm holes of aluminum oxide. Inside these holes, the authors determined that the horizontal etch rates slowed to an amount of 19% compared to the vertical rate when short process times were used. For process times operating in the saturation mode of the ALE process, horizontal etch rates per cycle could be sped up to 71% of the vertical rate but never reached parity with the latter. The authors propose a simple mechanism for explaining the anisotropy dependence on process step time and applied a reduced-order algorithm to model it. In this model, the authors introduced fitting parameters for surface modification depths and reaction times to match the experimentally found etch results. Conclusions could be drawn regarding topological hindrance or tortuosity for reactants to reach surfaces in shaded areas under the mask and for reaction by-products to escape from these locations and the impact on etch rate. In addition, the authors recognize that this mechanism could explain the unwanted depth dependence of the etch rate per cycle in high aspect ratio structures.

Thermal etching of AlF3 with dimethyl-aluminum chloride (DMAC) and thermal isotropic atomic layer etching (ALE) of Al2O3 with alternating anhydrous hydrogen fluoride (HF) and DMAC steps were studied. DMAC vapor etches AlF3 spontaneously at substrate temperatures above 180 °C. The thermal etching reaction of AlF3 with DMAC exhibited no self-limitation and showed a linear dependence on DMAC pressure. The authors determined an activation energy of 1.2 eV for this reaction. When Al2O3 is fluorinated, DMAC removes the fluorinated layer partially. The etch amount per cycle (EPC) in thermal isotropic ALE of Al2O3 with HF/DMAC is primarily determined by the fluorination step placing significant importance on its design. Fluorination with HF gas was found to be more effective and repeatable than with NF3. Plasma fluorination is faster and provides higher EPC, but the selectivity to Si3N4 or SiO2 mask materials is compromised. For pressures between 10 and 110 mTorr and a substrate temperature of 250 °C, thermal ALE of Al2O3 with HF/DMAC was found to have a very high selectivity to SiO2 and amorphous silicon. HfO2, however, etched with similar EPC as Al2O3.

A conceptual framework is introduced to gain insights into performance benefits and challenges of directional and isotropic Atomic Layer Etching (ALE).

In this paper, we report on plasma assisted thermal Atomic Layer Etching (ALE) of Al2O3. The surface was modified via a fluorine containing plasma without bias power. The removal was accomplished by a thermal reaction step using tin-(II) acetylacetonate Sn(acac)2. After a few cycles, material removal stopped and growth of a Sn-containing layer was observed. Insertion of a hydrogen plasma step was found to remove the Sn layer and a continuous material removal of 0.5 A/cycle was measured. The results show that plasma assistance can be used to realize thermal ALE of Al2O3. Specifically, plasma can be used both in the fluorination step and to keep the surface free from contaminations.

Isotropic atomic layer etching (ALE) is increasingly becoming an option and even a necessity for modern chip manufacturing. Especially for application such as 3D-NAND memory, the ability to perform isotropic etches will be a critical addition to the established suite of reactive ion etching. In this work, we have characterized the reaction of aluminum oxide (Al2O3) via the vapor-based DMAC ligand exchange mechanism in nanometer-size structures in which the oxide is buried below a silicon nitride mask. In the oxide, we measured vertical and horizontal etch rates and found that the etch showed some residual anisotropy even though all elements of the etch itself (flow, no plasma) were none-directional. We applied a simple Monte-Carlo simulation to show that anisotropy is caused by a delay in the onset of the horizontal etch beneath the mask and by molecular scattering effects in the vapor phase above the nano-structures. We are contrasting these results with experimental findings in structures without an anisotropy of the etch.

Following Moore’s Law, feature dimensions will soon reach dimensions on an atomic scale. For the most advanced structures, conventional plasma etch processes are unable to meet the requirement of atomic scale fidelity. The breakthrough that is needed can be found in atomic layer etching or ALE, where greater control can be achieved by separating out the reaction steps. In this paper, we study selective, directional ALE of silicon using plasma assisted chlorine adsorption, specifically selectivities to bulk silicon oxide as well as thin gate oxide. Possible selectivity mechanisms will be discussed. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0031506jss] All rights reserved.

This paper investigates the interest of synchronous pulsed plasmas to etch silicon in HBr/O2 chemistries. Using mass spectrometry, ellipsometry and angle resolved X-ray photoelectron spectroscopy, we demonstrate that the radical concentration in the plasma, the etch rate and formation of passivation layers, can be controlled by the RF pulse parameters (frequency and duty cycle). Accordingly, pattern profiles are improved, selectivity to the mask is increased and the silicon recess is reduced from 4 to 0.8 nm when the HBr/O2 plasma lands on thin silicon oxide.

Plasma etching or Reactive Ion Etching (RIE) is the workhorse for patterning of semiconductor devices since the early 1980-ies when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance which were unimaginable back then. At the same time, etching technologies such as Atomic Layer Etching (ALE), radical, dry vapor and Ion Beam Etching are finding their way into manufacturing for certain applications. We will present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies which use just one kind of etching species, such as neutrals, radicals or ions. Then we combine these techniques into cycling processes which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, and an outlook into the future of semiconductor device etching will be given.

Ion Beam Etching (IBE) is emerging as the technology of choice for patterning of advanced embedded MRAM devices ( Sub 1ppm short fail patterning results have been obtained with optimized IBE and encapsulation processes.

Atomic Layer Etching (ALE) transitioned to manufacturing because of unique performance benefits which come from self-saturation of the steps and the use of very low ion energies or just thermal means to remove material. The former property gives uniformity across all lengths scales on the wafer. Reduced aspect ratio dependent etching (ARDE) and surface smoothness are very attractive benefits. Low level removal energies deliver selectivity which is a key requirement for etching with atomic scale fidelity. In this talk, a conceptual framework for directional and isotropic ALE will be compared to other etching technologies for semiconductor devices. Recent experimental and theoretical results as well as applications examples will be presented to illustrate the concepts.

Atomic Layer Etching (ALE) is a cyclic process comprised of a self-limited surface modification step followed by a self-limited step to remove the modified layer. Based on this definition, there are several approaches to realize and classify ALE. For instance, one can distinguish between directional and isotropic ALE depending on whether the removal of the activated layer is accomplished by ion bombardment or thermal energy. Thanks to such salient performance benefits as uniformity across all length scales and selectivity, atomic layer etching is being proliferated in production. Directional ALE was the first process to go into production because most critical etch applications require directionality. Isotropic ALE is an emerging branch based on chemical reactions akin to those uses in thermal ALD. The term “isotropic” means that the etch proceeds in all directions. This property is particularly valued in vertical device integration where materials need to be removed from vertical and concealed surfaces. In this talk, a conceptual framework for directional and isotropic ALE will be introduced to explain the performance benefits and limitations of both technologies. Experimental and theoretical results as well as applications examples will be presented to illustrate the concepts.

Plasma assisted atomic layer etching (ALE) has recently been introduced into manufacturing of 10 nm logic devices. This implementation of ALE is called directional ALE because ions transfer momentum to the etching surface during the removal step. Plasma assisted directional ALE can be described as sputtering of a thin modified layer on the surface of the unmodified material. In this paper, the authors introduce a collision cascade based Monte Carlo model based on sputtering theory which has evolved for over 50 years [P. Sigmund, Thin Solid Films 520, 6031 (2012)]. To test the validity of this approach, calculated near threshold argon ion sputtering yields of silicon and chlorinated silicon are compared to published experimental data. The calculated ALE curve for Cl2/Ar ALE of tantalum is in good agreement with the experiment. The model was used to predict the presence of salient sputtering effects such as ion mass and impact angle dependence, as well as redeposition in directional ALE. Finally, the author...

Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.

Surface oxidation states of transition (Fe and Co) and noble (Pd and Pt) metals were tailored by controlled exposure to O2 plasmas, thereby enabling their removal by specific organic chemistries. Of all organic chemistries studied, formic acid was found to be the most effective in selectively removing the metal oxide layer in both the solution and vapor phase. The etch rates of Fe, Co, Pd, and Pt films, through an alternating plasma oxidation and formic acid vapor reaction process, were determined to be 4.2, 2.8, 1.2, and 0.5 nm/cycle, respectively. Oxidation by atomic oxygen was an isotropic process, leading to an isotropic etch profile by organic vapor. Oxidation by low energy and directional oxygen ions was an anisotropic process and thus results in an anisotropic etch profile by organic vapor. This is successfully demonstrated in the patterning of Co with a high selectivity over the TiN hardmask, while preserving the desired static magnetic characteristic of Co.

An organic chemical etch process based on tailoring the surface oxidation state was found to be effective in realizing directional etch of magnetic and noble metals for their integration and application in magnetoresistive random access memory devices. Using Pt, a noble metal, as a test case, plasma treatments with sulfur- and oxygen-based chemistries were able to oxidize Pt0+ to Pt2+ and Pt4+, which can be effectively removed by selected organic chemistries. The most effective control of the surface oxidation states of Pt was achieved with an O2 plasma, which was then applied with similar effectiveness to other transition and noble metals. By quantifying the reaction rate, the oxidation of transition metals (Fe and Co) was shown to follow an inverse log rate law, while that of noble metals (Pd and Pt) follows a parabolic rate law. This work highlights the importance of the surface oxidation states of magnetic and noble metals in enabling directional etch by organic chemistry.

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters [J. Appl. Phys. 50, 5 (1979)]. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms of energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bu...

As the IC industry approaches devices with half pitches below 10 nm, etching requires atomic scale fidelity because the device dimensions and their allowed tolerances are of the same order of magnitude as the inter-atomic distances in the crystal lattice. Atomic Layer Etching is emerging as a solution and plasma assisted or directional ALE is being adopted in the manufacturing of integrated devices /1/. Separation of the etching process into single unit processes allows to apply the large body of knowledge in surface science to improve fundamental understanding. In this talk we will focus on the fundamental processes at the wafer surfaces during etching of various materials with different ALE approaches. Strategies to obtain low physical and chemical surface damage will be presented. 1. K.J. Kanarik, T. Lill, E. Hudson, S. Tan, S. Sriraman, J. Marks, V. Vahedi, R.A. Gottscho; J. Vac. Sci. Technol. A 33, 020802 (2015)

As critical dimensions decrease, key dimension-related dielectric etch challenges emerge, including via and trench uniformity and etch depth profile. The transition to ultra-low-k films such as BDIII (Black Diamond; k=2.55) dielectrics requires consideration of film sensitivity to compositional modification, polymer interactions at pores, and the effect of diffusion. Use of N2/O2 plasma at 60 ˚C to modify the M1 trench profile has been demonstrated to lower the RC delay by 14% as compared to traditional CO2 plasmas at 60˚C. Use of a DHF solution to clean the etching residue in the dual damascene structure results in >97% yield with a tight range of via chain resistance.

Impact of C 60 + ions onto an epitaxially grown crystalline fullerite target is studied at a primary kinetic energy of 275 eV as a function of the angle of incidence. Scattered ions are investigated by velocity selective time-of-flight mass spectrometry at a fixed scattering angle of 140 o . In addition to scattering of intact C 60 + ions we also see desorbed C 70 + as well as larger ions C 100 + to C 130 + arising from reactive processes (fusion, coalescence). The velocity distribution of the receding C 60 + ions reveals a range of processes from nearly elastic to fully inelastic. The angular dependence exhibits rich structure. This may be attributed to rainbow scattering, as confirmed by a simple classical trajectory calculation

In this article, we have performed detailed investigations of the 193 nm photoresist transformations after exposure to the so-called HBr and Ar plasma cure treatments using various characterization techniques (x-ray photoelectron spectroscopy, Fourier transformed infrared, Raman analyses, and ellipsometry). By using windows with different cutoff wavelengths patched on the photoresist film, the role of the plasma vacuum ultraviolet (VUV) light on the resist modifications is clearly outlined and distinguished from the role of radicals and ions from the plasma. The analyses reveal that both plasma cure treatments induce severe surface and bulk chemical modifications of the resist films. The synergistic effects of low energetic ion bombardment and VUV plasma light lead to surface graphitization or cross-linking (on the order of 10 nm), while the plasma VUV light (110–210 nm) is clearly identified as being responsible for ester and lactone group removal from the resist bulk. As the resist modification depth de...

With the continuous scaling down of the critical dimensions (CDs) of semiconductor devices, the linewidth roughness (LWR) becomes a non-negligible parameter that needs to be controlled within 1nm (at 3σ) for the 32nm node and beyond. In this article, the authors have used a CD-atomic force microscopy to investigate the evolution of the LWR during the subsequent lithography and plasma etching steps involved in the patterning of polysilicon transistor gates. The authors demonstrate that the LWR present on the etching mask [photoresist/bottom antireflective coating (BARC), SiO2 or amorphous carbon hard masks] right before the gate etching is transferred into the polysilicon during the HBr∕Cl2∕O2 gate etching step. Thus, the final polysilicon LWR directly is strongly dependent on the lithography and plasma etching steps preceding the gate etching step. The authors show that by applying plasma treatment to minimize the resist mask LWR prior to all the other etching steps or by optimizing the BARC opening plasm...

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.

Summary form only given. We have investigated the characteristics of VHF capacitively coupled plasmas produced in a modified applied materials chamber. The chamber had a 14-inch diameter upper electrode (source) that was driven at 10 to 160 MHz and a 300 mm diameter electrostatic chuck with a ceramic process kit that was driven at 13.56 MHz (bias). Diagnostics employed include RF diagnostics to measure the voltage and current, Bdot probes to measure the spatial magnetic fields, a microwave interferometer to measure the line-integrated electron density, a hairpin microwave resonator to measure the spatially resolved electron density, absorption spectroscopy to determine the argon metastable temperature and density, laser induced fluorescence (LIF) to determine the spatial distribution of the excited species, and spatially resolved optical emission. Scaling of the plasma parameters with frequency, power and pressure, and implications to energy deposition models will be discussed

High aspect ratio silicon trench etch is a key process to manufacture trench capacitor DRAMs. The capacitance is directly proportional to the surface of the capacitor. Shrinking to the next technology required a similar capacitance while the corresponding CDs are reduced. To ensure sufficient capacitance the aspect ratio has to be increased. The existing trench etch reactor was not capable to reach the required aspect ratio due to its limited selectivity to the oxide hard mask. Thus, new plasma reactor hardware had to be developed and evaluated. This work summarizes and compares the process performance of the new with the previously used hardware.

Results of a tungsten silicide/poly-Si gate etch process based on a Cl/sub 2//NF/sub 3//HBr silicide step are presented. The addition of fluorine to the main etch suppresses the formation of polymers in the reactor chamber. HBr allows the control of the sidewall passivation of the microstructures. A very thin yet robust sidewall layer is desired to achieve ultimate critical dimension (CD) control without sacrificing profile shape. CD microloading (i.e. the difference in the CD bias for nested and isolated lines) is minimized by operating at elevated cathode temperatures. The grain structure of the silicide film determines the roughness of the silicon etch front prior to approaching the gate oxide. In-situ reflectometry and atomic force microscopy have been used to analyse the mechanism of gate oxide texturing and punch through. Reflectometry can be used to predict the exposure of the gate oxide and to switch early enough to a very selective etch step that clears the poly-Si.

We present results of an interferometric endpoint prediction technique for use in plasma etching of various gate structures in advanced CMOS device fabrication. Etch experiments were carried out in a production high-density plasma source (Decoupled Plasma Source). The prediction technique been successfully to many and types of structures commonly found in integrated circuit manufacturing. The ability to predict endpoint and avoid breakthrough of gate oxides as thin as 19 /spl Aring/ has been investigated. The flexibility of the endpoint algorithm together with the external trigger controller are demonstrated to be crucial for successful endpoint prediction.