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The high-NA angle-resolved scatterometer YieldStar 1250D, with a small 12x12μm2 inspection area, has been used to inspect CD variation After Develop (ADI) and After Partition/Final Etch (APEI/AFEI) on various layers and features of a HVM DRAM process. During recipe set-up, CD-SEM data were used to verify full recipe quality. The high sampling density enabled by the small inspection area and high speed of the YieldStar angle-resolved scatterometer could be used to reveal various kinds of CD variations. An intra-field control-loop with scanner dose corrections was tested, using very dense ADI and APEI measurements, 400ppf, 4fields. This strategy demonstrated a 21% improvement in intra-field CDU, in line with expectations from predictions. Inter-field control loops with different strategies have been simulated for APEI CD control. To capture all variations in the inter-field fingerprints a dense sampling, 24ppf full wafer, in combination with a dynamic, context-based control strategy, appeared to be necessary. An improvement of 30% of the wafer CDU (excluding the intra-field) is feasible. For the Self-Aligned Double Patterning process, essential for the dense DRAM cells, the CD variation at APEI contributes to pitch-walking at final etch. Pitch walking is an alternating OV error, therefore these control strategies will also contribute to improvement of the OV control budget.

Spacer multi patterning process continues to be a key enabler of future design shrinks in DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main features remains high priority for multi patterning technology and requires improved metrology and control solutions. In this paper Spacer Patterning Technology is evaluated using an angle resolved scatterometry tool for both intra field control of the core CD after partition etch (S1) and interfield pitch-walking control after final etch (S1-S2). The intrafield measurements were done directly on device using dense sampling. The inter-field corrections were based on sparse full wafer measurements on biased OCD targets. The CDU improvement after partition-etch was verified by direct scatterometer and CD-SEM measurement on device. The final etch performance across wafer was verified with scatterometer on OCD target. The scatterometer metrology in combination with the control strategy demonstrated a consistent CDU improvement of core (S1) intrafield CD after partition etch between 23-39% and 47-53% on interfield pitch-walking (S1-S2) after final etch. To confirm these improvements with CD-SEM, oversampling of more than 16 times is needed compared to scatterometer. Based on the results it is concluded that scatterometry in combination with the evaluated metrology and control strategy in principle qualifies for a spacer process CDU control loop in a manufacturing environment.

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn’t be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Holistic lithography is needed to cope with decreasing process windows and is built on three pillars: Scanner Tuning, Computational Lithography and Metrology & Control. The relative importance of stability to the overall manufacturing process latitude increases. Overlay and focus stability control applications are important elements in improving stability of the lithographic process. The control applications rely on advanced control algorithms and fast and precise metrology. To address the metrology needs at the 32 nm node and beyond, an optical scatterometry tool was developed capable of measuring CD, focus-dose as well as overlay. Besides stability and control of lithographic performance also scanner matching is a critical enabler where application development and metrology performance are key. In this paper we discuss the design and performance of the metrology tool, the focus and overlay control application and the application of scatterometry in scanner matching solutions.

The extension of ArF lithography through reduced k1, immersion and double patterning techniques makes lithography a difficult challenge. Currently, the concept of simple linear flow from design to functional photo-mask is being replaced by a more complex scheme of feedback and feed-forward loops which have become part of a complex computational lithography scheme. One such novel lithography concept, called "holistic lithography", was recently introduced by ASML, as a scheme that makes the lithography process a highly efficient solution for the scaled down geometries. This approach encourages efficient utilization of computational lithography and the use of feed-forward and feed-back critical dimension (CD) and overlay correction loops. As sub-nanometer feature dimensions are reached for 3x nodes, with k1 reaching the optics limitations, Mask error enhancement factor (MEEF) values grow fast, thus making mask uniformity fingerprint and degradation throughout its life time a significant factor in printed CDU on the wafer. Whereas the consensus is on the need for growing density of intra-field data, traditional critical dimension scanning electron microscope (CDSEM) Feed backward loops to the litho-cell become unsuitable due to the high density CD measurement requirements. Earlier publications proposed implementing the core of the holistic lithography concept by combining two technologies: Applied Material's IntenCDTM and ASML DoseMapper . IntenCD metrology data is streamed in a feedforward fashion through DoseMapper and into the scanner, to create a dose compensation recipe which improves the overall CDU performance. It has been demonstrated that the IntenCD maps can be used to efficiently reduce intra-field printed CDU on printed wafers. In this paper we study the integration concept of IntenCD and DoseMapper in a production environment. We implement the feed-forward concept by feeding IntenCD inspection data into DoseMapper that is connected to ASML's TWSINCANTM XT:1900i scanner. We apply this concept on printed wafers and demonstrate significant reduction in intra-field CDU. This concept can effectively replace the feedback concept using send-ahead wafers and extensive CDSEM measurements. The result is a significant cost saving and fab productivity improvement. By routinely monitoring mask-based CDU, we propose that all photo-induced transmission degradation effects can be compensated through the same mechanism. The result would be longer intervals between cleans, improved mask lifetime, and better end of line device yield.

Here we present both simulation and experimental results that show the effect of changes in laser light source bandwidth (E95) on CD Iso-Dense Bias. For the 55nm Technology Node Device, we have shown that E95 stability of less than 0.11pm is required in order to maintain OPE variation to within 2nm. In addition, we also verified another method to adjust for OPE variations that occur when E95 fluctuates. The Contrast Adjustment method is an effective function to adjust for OPE variation due to E95 fluctuation; it has been shown to maintain OPE variation less than 1.5nm. Furthermore, for the 45nm Technology Node Device, we have demonstrated that E95 stability of less than 0.07pm is required to maintain OPE variation to within 1nm. The bandwidth performance of the latest laser light source exhibits E95 stability less than 0.03 pm, thereby showing that the OPE variation due to E95 can be kept to under 1nm.

In hyper NA system, specific illumination combined with polarization can be used as one of major RET techniques. Polarization at high NA dry system is also regarded as important technology to bring improvement of very low k1 process. The benefits of polarization on repeated structure are very well known. However we also need to understand the effect on random pattern in peripheral region to adopt polarization technology successfully into real devices. Memory device such as DRAM and NAND Flash has repeated cell structure and also loose pattern in peripheral region. In this study two kinds of polarization function will be applied to real memory devices and the polarization behavior on various patterns in peripheral circuit will be analyzed through actual printing process using 6% attenuated PSM at ArF high NA dry system. The printed result will be compared on random patterns through in-line metrology tool and process guideline including OPC treatment will be discussed based on this study, especially with regard to ID bias.

As the device integration and relating lithography process progressively increasing in complexity for each new technology node, there is a growing need for a more integrated approach to process control. There are several insitu metrology sensors in ASML scanners that can be used to improve not only the scanner equipment and lithography process stability but also to compensate for other process modules' fingerprint to achieve an overall tighter process control and improved device performance. In this paper, we will describe the functionality of some of the scanner's insitu metrology sensors, such as the ILIAS for lens performance, and the methods of it usage to not only control the scanner's lens stability but also to improve the lithographic process performance such as the overall device critical dimension uniformity (CDU). Furthermore, we will introduce an integrated methodology of using scanner exposure dose, known as Dosemappertrade to compensate for other process module's systematic fingerprint to achieve an improved device electrical performance. This was demonstrated in an improvement in the intra-wafer ring oscillator's stage delay using the dose compensation [1]. Finally, we will show the potential of using another insitu detector, the spot sensor, to feed forward the reticle's CD fingerprint (known as Spot sensor Enabled Reticle Uniformity Measurement or SERUM) to the scanner and take the advantage of using the Dosemapper's functionality to improve the intrafield CDU.

One of the crucial factors to take mostly into account the development and production of 130 nm node in low k1 DRAM process is the lens aberration sensitivity control of optical lithographic tools. To meet the required specification these impact of lens aberration resulting from reducing process window caused by pattern deformation, CD uniformity, CD asymmetry, and pattern shift etc. should be understood and considered. In this study, we mainly focused on the aberration sensitivity control for the DRAM isolation layer that is very sensitive to odd components such as coma and three-foil etc. There are a few methods to do this, but the application of extreme sigma setting that is the powerful manner to improvement of asymmetric pattern and layout rotation were examined. It was confirmed that the simulated image and real patterning results for left-right CD difference came from aberrated lens are well matched. In addition, why is the extreme sigma setting more effective than standard settings was investigated with analysis of diffraction patterns on pupil filling of projection lens optics combined with Zernike coefficients phase map.

As resolution shrinks, also the demands for litho CD Uniformity are becoming tighter. In replicating the mask pattern into photoresist, a sequence of modules within the patterning cluster (coat, expose, develop, etch) is responsible for CD non-uniformity. So far, the strategy has been to make the contribution of each of these modules as small as possible. The CD Uniformity can be improved in a more efficient way by compensating the various error sources with adapted dose profiles on the scanner. An inventory is made of the requirements for this compensation mechanism. In more detail a description is given how the scanner can apply these dose corrections. With experiments, the feasibility of the concept is proven. Improvements in CD Uniformity over 5nm are demonstrated, both on test structures as well as on real device layers.