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AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selective AlOx deposition involves multistep process including surface treatment, selective Self-Aligned Molecules (SAM) bonding to inhibit Cu metal surface, and the selective growth of AlOx on top of SiCOH dielectric using Chemical vapor deposition process with various precursors and process conditions below 300°C. Thin selective AlOx of 4–6 nm thickness show excellent selectivity on SiCOH over Co capped Cu-SiCOH patterned structures with various spacing. The Via Chain electrical yields were measured on 32 nm pitch structures by AlOx selective deposition and are comparable to the established FAV process by Cu wet recess. This indicates that the Selective AlOx deposition process is highly selective on SiCOH dielectric surface without defect formation in the Co Capped Cu surfaces.

Mechanically robust low k C-rich SiCN and pSiCN dielectrics with excellent built-in Cu oxidation and diffusion barrier have been developed and evaluated as potential alternative low k Interlevel dielectrics for Cu interconnects. The novel low k dense C-Rich SiCN (k=3.3) and lightly porous C-Rich SiCN (k=2.8) films have high modulus (E~> 15-30 GPa) and significantly lower Plasma Induced Damage (PID) as compared to typical pSiCOH (k~2.4-2.7) dielectrics. The excellent Cu diffusion barrier properties of these SiCN dielectrics enable the use of thinner metallic Cu barriers that resulting in larger Cu line’s volume, reduced resistance and overall improved RC in sub-50 nm pitch interconnects without TDDB and EM reliability penalty.

As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

Particle defects in the form of foreign material (FM) are a common occurrence in semiconductor manufacturing. This work discusses the strategies used to detect the source of FM particles in a room temperature oxide furnace. FM particles were measured during the 215 A oxide recipe qualification and showed counts as high 603 particles, exceeding the limit of 130 particles. Common sources of FM particles such as hardware contamination and process recipe conditions were ruled out as the root cause. It was discovered that the rotation stop position of the boat during deposition for the 215 A recipe put the pedestal alignment pin (attached to the elevator) in front of the backfill N2 injector during the backfill sequence of the recipe. The high flow of 30 slm during the backfill caused the pin to vibrate and produce particles. The probability of stopping at this position for a given recipe is 1 out of 360. The final solution was to make all recipes stop at a home position to guarantee the pin does not stop in front of the N2 injector.

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

The scaling limit of plasma enhanced chemical vapor deposited (PECVD) ultrathin(5-35 nm) silicon carbon nitride (SiCNH) dielectric as an oxidation and Cu diffusion barrier for damascene process is explored. The SiCNH cap's electrical properties, oxidation barrier performance, and the compositional depth profile analysis results showed that the scaling of the SiCNH cap is limited to 25 nm thickness. Without additional changes in current optimal SiCNH cap, 25 nm is the minimum required thickness for a reliable SiCNH cap in sub-30 nm Cu BEOL devices.

EXTENDED ABSTRACT Continued integrated circuit scaling deeper into the nanoscale regime has provided improved performance through shrinking of the Front-End-of-Line (FEOL) device and Back-End-of-Line (BEOL) interconnect. With scaling, resistance-capacitance (RC) delay is an increasing challenge, limiting overall product performance. Capacitance reduction is therefore vitally important for device performance in both the FEOL and BEOL device structure. Conventional capacitance reduction methods for FEOL and BEOL while maintaining yield and reliability have required significant material innovations such lower-k cap and bulk dielectrics with required mechanical, structural, electrical and other properties. To improve capacitance, other innovations in device structure and process integration such as Air Gap and Air Spacer are also needed (1-2). The air spacer (FEOL) and air gap (BEOL) structures require novel process technology approaches such as pinch off deposition to optimize the capacitance reduction while maintaining yield and reliability. In this paper, we present an overview of material and process technology requirements for FEOL air spacer (1) and BEOL air gap (2) formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume as typically show in figure 1. The void dimension and volume in airgap structures can be controlled with various dielectric deposition processes and materials as shown in Figure 1: (a) Long and wide voids for optimal capacitance reduction. (b) Short and wide voids for improved process fabrication and integration. (c) Short and narrow voids for better sidewall protection and device reliability but with a smaller capacitance reduction. The overall void dimension and type of dielectric material are strongly related to the total device capacitance reduction and reliability. Significant capacitance reduction with good reliability has been achieved through material, process and structural/architectural optimization with the pinch off deposition process approach on current 10 nm device structures as shown in figure 2 (FEOL Air spacer) and figure 3 (BEOL Air Gap). This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities References 1) K. Cheng, S. Nguyen et al. International Electron Device Meeting, Proceeding Vol. 2016, paper 17.1, pp.444-447. San Francisco, USA 2) C. Penny, S. Gates, B. Peethala, J. Lee, D. Priyadarshini, S. Nguyen, P. McLaughlin, E. Liniger, C.-K. Hu, L. Clevenger, T. Hook, H. Shobha, P. Kerber, I. Seshadri, J. Chen, D. Edelstein, R. Quon, G. Bonilla, V. Paruchuri, and E. Huang, International Interconnect Technology Conference, Proceed. Volume, paper 2.2, May 16-18,2017, Taipei, Taiwan. Figure 1

The metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra low-k dielectrics to reduce RC delay and cross talk in devices. For the 90nm to 14 nm CMOS device nodes, conventional silicon nitride was replaced by new dielectric barrier low k materials such as SiCN, C-Rich SiCN and SiNO (1-6). As devices scale down to x film deposited by plasma enhanced CVD with TMS+NH3 is still robust down to around 15-20 nm thickness range. This paper presents the development of the second generation robust Low Hydrogen SiCN to enable cap thickness reduction to EXPERIMENT The low hydrogen SiCNx films were deposited in a commercial high throughput production worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH3) + Hydrogen precursors with excellent uniformity (1 sigma < 1 %). The as-deposited films were analyzed using various electrical , mechanical and chemical analyses to study the film's properties and compositions, Table 1. An oxidation resistance test (6) was done after the barrier film/copper blanket stack was annealed at 310°C for 24 hours in ambient atmosphere. Multi-level 7nm copper interconnect structures were built for Electro-migration (EM) and Time Dependent Dielectric Breakdown (TDDB) reliability measurement (150-300°C). RESULTS and DISCUSSION Table 1 summarizes SiCN and Low H SiCN cap film properties and device performance. Overall, the low H SiCN cap has better electrical, mechanical, and device reliability performance than the standard SiCN cap. The low H SiCN film has higher density, modulus, hardness and significantly higher compressive stress, both as-deposited and post 5 minutes direct UV cure. Compositional analysis shows that PECVD SiCNx cap films deposited with the addition of hydrogen precursor actually have less hydrogen than films deposited without hydrogen under the same optimized deposition condition. Film deposition rates decrease slightly at higher hydrogen flow rate in the TMS+NH3+H2 precursor chemistry. The reduced deposition rate and the hydrogen reduction in the film’s bulk are attributed to the increase removal (etching) of weakly bonded -Si-Hx and -N-Hy species in the film during the plasma deposition process. FTIR analysis shows that Si-C and Si-N bonding density increases in the low H SiCN dielectric, which is consistent with the increase in film density, modulus and harness. A minor reduction in the dielectric constant, similar breakdown voltage and reduced leakage are observed for the low H SiCN cap. Figure 1 shows a typical Scanning Transmission Electron Micrograph (STEM) of a 3nm Co/10 nm Low H SiCN cap on a Copper Metal2 7nm interconnect structure. This Cu/Co/Low H SiCNxcap structure achieves 4-10X better EM/TDDB reliability versus a similar structure with the standardcap (Table 1). A Scanning Electron Micrograph (SEM) of the patterned surface after annealing at 310°C for 24 hours in ambient atmosphere (Figure 1) shows that the 10 nm Low H SiCN cap has excellent Cu Oxidation properties with no sign of Cu Oxidation. CONCLUSIONS Low hydrogen SiCN dielectrics with improved mechanical, oxidation and Cu diffusion barrier properties versus standard SiCN were deposited using TMS, NH3 and H2. The new robust low hydrogen SiCN dielectric cap film showed a significant increase in Si-C and Si-N bonding density and a reliability performance improvement in 7 nm Cu interconnect structures at Acknowledgment This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. The author would like to thank B. Peethala for some analysis and A. Grill for discussion. REFERENCES [1] L. Xia, M. Naik, H. Xu, V. Zubkov, R. Bhatia, C. Peterson, M. Spuller, and H. M’Saad, Proceeding of Advanced Metallization for Devices and Circuits, (2006) pp. 169. [2] S.G. Lee et al, Jpn. J. Appl. Phys., 40, 2663 (2001). [3] Al Grill, Steve Gate, Son Nguyen, D. Priyadarshin, E Tood Ryan; Appl. Phys. Rev. 1, 011306 (2014). [4] Son V. Nguyen et al., Electrochem. Soc. Transaction 2014, Volume 61, issue 3, pp.17-28. [5] C.Yang et al., IEEE Electron Device Letter, Vol 33, No, 4, pp.588-560 (2012). [6] Son Nguyen et al., Electrochem. Soc. Transaction. 2010, Volume: 33, Issue: 12, pp.137-145. Figure 1

The initial transient (ITS) phenomena in plasma enhanced Chemical Vapor Deposition (PECVD) process was identified in early 1980’s (1). This ITS phenomenon has impact on the bonding structure and composition of plasma deposited silicon nitride (1) and amorphous silicon (2) films at the initial film-substrate interface. When the deposited film is in micron thickness, the ITS impact is generally smaller. The shrinking of semiconductor devices and the corresponding push to increase device density is continuing in the quest for improved performance of integrated circuits. Nano scale thickness low temperature plasma CVD dielectric films such as silicon nitride and silicon carbon nitride used as cap materials (3) for Cu interconnects that are expected to reach to sub-10 nm dimension next few years. The compositional variation in PECVD films at the interface by ITS which had a relatively small impact in past semiconductor technologies is becoming a significant factor in film’s properties as we scale film thickness down to sub-10nm. In this paper, we will present in detail the impact of the initial transient plasma in CVD process on the ultrathin nano thick cap and-low k dielectric films that are being used for advanced device interconnect fabrication, We will show that we can modify the current standard PECVD process to alleviate the impact of ITS phenomena. Some ITS impact on nano thick film are: a) PECVD silicon nitride / silicon carbon nitride dielectric cap films are normally deposited with a mixture of silane/ammonia or other carbosilane/ammonia precursors. The initial breakdown of silane is strongly affected by the plasma conditions and the dissociation thermodynamic of the precursors. Deposition rates can be different on Cu versus dielectric surfaces due differences in charging effects (see Figure 1). Additionally, the silane molecule is relatively unstable and more reactive as compared to ammonia, and typically dissociate rapidly first to form more conformal SiHx deposition radicals before the plasma reaches a steady state. Subsequently, PECVD with SiH4/NH3 precursors will normally produce a Si-rich silicon nitride composition at the interface. Silicon carbon nitride films can be deposited from more stable carbosilane precursors. In this case, the thickness of the Si-rich interface zone can be reduced, and a C-rich film surface may be deposited under specific deposition condition. This modulation may be exploited to control electrical (k, breakdown/leakage) and adhesion properties of the film for Cu low k interconnect structures. For a very thin dielectric cap deposited on a patterned structure of Cu and ultra-low k dielectric, the film thickness deposited on Cu versus the dielectric surface will be slightly different due to the differential local plasma charging effect during initial transient deposition period as shown in fig 1. This deposition rate difference will impact the film’s barrier and electrical properties, gap fill performance and subsequent in Cu-low k fabrication. In this case, plasma ITS charging is the principle mechanism that cause differences in film’s thickness. b) For typical PECVD SiN deposition process, the initial dissociation of SiH4 and/or NH3 will create reactive species that subsequently etch the deposited ultra-low k pSiCOH dielectric surface. These reactive species can produce substantial damage to pSiCOH, increase dielectric constant and subsequently poor reliability in final electronic devices. This damage can be reduced significantly by using an initially low rf plasma power and then increasing to a higher rf plasma power for the remainder of the deposition (4). ITS negative impact to devices and mitigation method will be discussed. c) For ultrathin cap films for Cu interconnects, such as SiN, variations in film composition at the interface will cause significant variation in electrical properties and conformality. To mitigate the ITS effect, a cyclic, multi-step deposition process utilizing plasma surface treatment was developed. A multilayers film with better conformality and consistent film’s properties was achieved. Using this novel cyclic process, high quality dielectrics SiN and SiNO at sub-10 nm thickness can be deposited consistently and reproducibly for Cu-low k interconnect fabrication as showed in Figure 2. In summary, the ITS phenomena on plasma CVD, its impact in nano thick film fabrication and methods to mitigate the ITS’s negative impact will be presented in the paper. References [1].Son V. Nguyen and P. Pan, Applied Physics Letters, V54 (2), pp.134-136 (1984). [2] Y.Nakayama, T.Kuchi, and T. Kawamura, J. Appl. Phys. 62, 1022 (1987). [3] Son Nguyen, et al., Electrochemical Society Fall Proceed., paper # 1685, Las Vegas, Nevada USA October 10-15, 2010. [4] Son Nguyen, et al., Electrochemical Society Fall 2011 Proceeding, Paper #1933, Boston, USA. Oct 9-15, 2011. Figure 1

High mobility channel materials such as Si1-xGex (x = 0.1-0.5) are important to achieve performance targets for FinFET devices at dimensions scaled beyond 14nm. Previously, flowable (FCVD) SiO2 deposition processes have been developed to achieve adequate fill for Shallow Trench Isolation in FinFET structures. However, the thermal budget for curing FCVD oxide with SiGe fins must be limited to avoid out-diffusion of Ge. This restricts the processing options for achieving a robust material which is compatible with subsequent wets processing steps. FCVD oxide deposition employs an amine-based silicon precursor which, upon exposure to NH3 radicals, forms short chain -Si-N-Si- oligomers with terminal Si-H or N-H bonds. These oligomers flow into and fill deep isolation trenches. Once the trenches are filled, it is critical to stabilize the film and initiate cross linking for densification to SiO2. To this end, a cure while still under vacuum, such as O3 oxidation, is commonly used before a subsequent furnace steam anneal. This paper describes an alternate curing process using broadband UV light to densify FCVD oxide. Material properties were studied using cure by microwave-powered Hg lamps at 10 degC with broadband (200-450nm) spectrum and compared to the existing O3 cure. To achieve the desired FCVD film properties, it is beneficial to remove -OH terminations during the post-dep cure to promote a dense final -Si-O-Si- matrix. Fig. 1 shows high frequency FTIR spectra from UV-cured FCVD oxide films as a function of UV power post-steam anneal. Data from O3 cured FCVD oxide is plotted for comparison. The spectrum from the non-oxidizing UV cure process shows lower peak intensities for –OH and H-OH stretch peaks. For promoting densification, UV curing is also effective in breaking N-H bonds. The number of NH/NH2 bonds is reduced with increasing UV power and a corresponding increase in Si-H bonding is observed. Figure 2 shows FTIR spectra of cured FCVD films treated with a subsequent steam anneal. The film with O3cure show more residual silanols (Si-OH) relative to UV cured films. Also, the -Si-O-Si- bonding peak is higher in UV cured films, suggesting a denser -Si-O-Si- network. During the steam anneal process, we observed that UV cured films densify more rapidly than O3 cured films. For anneals at 500°C, a dense SiO2 surface layer is formed, blocking further O2diffusion and leaving a less dense film below which has a higher wet etch rate (Fig. 3). This effect is evident in Fig. 4a where FCVD oxide has been recessed using an etching technique. The oxide between fins is weaker and has recessed more than the oxide in the field region outside of the array (see reference lines). A two-step steam anneal was then developed to achieve uniform properties through film depth: 400°C for 1 hour followed by 500°C for 2 hours. Fig 4b shows a structure with oxide annealed in this way and then recessed through etching; it was observed that the recess is now equivalent in the field and between fins. The impact of UV power on the cure process was also explored. Fig. 5 shows the WERR as a function of thickness for blanket O3 cured FCVD films and UV cured films after steam anneal. The UV cure again shows significantly lower WERR compared to O3 cure, with more densification and improved film uniformity through depth with increased power. Fig. 6 compares cumulative electrical breakdown behavior for O3 cured and UV cured films after steam anneal obtained using MIS structures. The UV cured films show a higher breakdown voltage (Vbd ~10MV/cm) relative to O3 cured films (~9MV/cm). Fig. 7 is a comparison of WERR between O3 cured film and UV cured film inside the narrow STI Trench Features. The films were steam annealed followed by 2x900°C-1min soak RTA in N2. Data shows 30% lower in-trench WERR for UV cure compared to O3cure. In conclusion, UV cure has been demonstrated as a means to provide improved FCVD quality over O3cure as measured by wet etch rate ratio, in blanket films and within trenches for STI applications. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. Figure 1

Continuous shrinking of the interconnect dimensions with each technology node requires reduction in RC (resistance-capacitance) delays. Reduction in capacitance requirement at 45nm node was met by introducing a k 2.4 inter-layer dielectric (ILD) at 2X metallization level [1]. However, the material was not readily extendable to next technology node because of the need for even higher modulus at the advanced nodes. Thus, there was a need to develop a new pSiCOH k 2.4 ILD with improved mechanical properties and damage susceptibility for back end of the line (BEOL) capacitance reduction. IBM/Alliance team has developed a number of pSiCOH films using a variety of precursors. Generally, the porous ultra-low k films are prepared by using a subtractive approach [2] in which the film is deposited using a mixture of skeleton and porogen precursor and then cured to remove the labile organic fraction [2]. An alternative to the above approach is to use a single precursor molecule consisting of skeleton with embedded porogen [3]. Developing a robust pSiCOH film with k < 2.55 has always been a challenge with this approach. This paper reports the development of a pSiCOH k 2.4 film deposited using a single precursor showing superior time dependent dielectric breakdown (TDDB) performance with lower integrated k (lower capacitance) as compared to the k 2.55 ILD pSiCOH film at 80 nm, 56 nm and 48 nm pitch. Octamethylcyclotetrasiloxane (OMCTS) precursor used for fabricating dense SiCOH dielectrics (k= 3.0-2.7) was used to form low k=2.4 film. The modified PECVD deposition conditions along with optimized UV cure resulted in k 2.4 ILD film deposited using a single precursor henceforth referred to as OMCTS Ex k 2.4. The new OMCTS Ex k 2.4 film has only slightly lower modulus as compared to the k 2.7 film deposited using OMCTS and O2 while showing comparable plasma induced damage (PID). PID was measured by thickness change after HF wet etch removed the damaged layer caused by standard plasma. In general, good TDDB performance is obtained by lowering porosity, increasing %C and reducing PID [4]. Each of these properties has been carefully optimized for new OMCTS Ex k 2.4 film by tuning the deposition and the UV cure conditions. Fig. 1 compares the RC performance for ULK k 2.55, ULK A k 2.4 (another PECVD k2.4 ILD) and OMCTS Ex k 2.4 film at 10 nm node. ULK A k 2.4 shows higher PID as compared to k 2.55 resulting in higher capacitance. In contrast, the OMCTS Ex k 2.4 retains the capacitance benefit because of the lower PID for this film. Table 1 compares the extracted k value for k 2.55 and the k 2.4 ILD’s at 80, 56 and 48 nm pitch. OMCTS Ex continues to show lower extracted k number with no significant increase in value with technology node scaling. Fig. 2 shows the TDDB performance of these ILD’s at 10 nm node. The higher carbon content with low plasma induced damage resulted in dramatically better TDDB for OMCTS Ex than other films. Important to note that the TDDB performance of this film is almost 15X better than the TDDB performance of k 2.55 and ULK A k 2.4 ILD. Conclusion A new advanced single precursor OMCTS Ex k 2.4 pSiCOH ILD film has been developed to meet the integration scaling and reliability requirements. The new OMCTS Ex k 2.4 film shows better film properties than the reference k 2.55 and other 2.4 films and retains capacitance benefit by demonstrating an overall lower integrated k value as compared to the k 2.55 ILD. Acknowledgement This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities. References [1] S. Sankaran, et al, “A 45 nm CMOS node Cu/low-k/ultra low-k PECVD SiCOH (k=2.4) BEOL technology”, Electron Devices Meeting, IEDM International, 2006 [2] A. Grill and C. Patel, “Ultralow dielectric constant pSiCOH films prepared with tetramethylcyclotetrasiloxane as skeleton precursor,” J. Appl. Phys., vol. 104, pp. 024113-9, 2008 [3] S. Nguyen, S. Gates, D. Neumayer, and A. Grill, US patent 7,491,658, 2009 [4] E.G. Liniger, et al, “TDDB extendibility of ULK materials to 14nm BEOL and beyond,” Adv. Metal Conf. 2012 Figure 1

Ever since Al(Cu) wires were replaced by Cu to reduce RC delay, the development of lower k dielectric materials has been a challenge to the back end of line (BEOL) process [1,2]. Copper wiring with low-k or ultra low-k (ULK) dielectrics for high-performance CMOS IC’s requires the use of a robust dielectric cap barrier to prevent inter- and intra-level Cu diffusion and also to maintain device yield and reliability. Plasma Enhanced Chemical Vapor Deposited (PECVD) low-k SiCNH and SiN are the predominant dielectric Cu diffusion caps used by the industry, in part due to the strong cap/Cu debond energies [3]. This paper will present the ultrathin ( We developed a new cyclic multilayer conformal ultrathin (8-14 nm) SiN deposition process to improve Cu CMP recess step coverage. This process includes cyclic low rf power plasma deposition of nano thick (~2 nm) SiN using Silane and Ammonia gases and then subsequent variable rf plasma power Nitrogen (N2) plasma treatment to minimize Cu sputtering and diffusion. The process is repeated in a cyclical manner until desirable film’s thickness is achieved, figure 1. The film deposition step and it enhanced STEM and EDX step coverage images for the post-CMP top corner Cu recess divot structure as showed in figure 2. The Triangular Voltage Test (TVS) and oxidation barrier (310 C, 24 hr exposure in air) evaluation showed this thin (10-14 nm thick ) SiN cap is a good oxidation and Cu barrier. Optimal cyclic SiN film has higher breakdown voltage and lower low leakage than standard SiCNH cap, even after exposure to UV cure, figure 3. As deposited, the SiN film has compressive stress in 500 MPa range. After UV direct UV exposure for 180 sec at 380C, the film’s stress still retain at 300 Mpa compressive. The cyclic SiN cap has excellent modulus of 159 GPa and hardness of 24 GPa. BEOL 80 nm pitch device electrical data showed that device reliability of the 10-12 nm SiN cap film are about comparable to standard 25 nm SiCNH cap but with significant lower device capacitance. SUMMARY A new generations of ultra-thin ( Acknowledgments: This work was performed by Alliance Teams at various IBM Research and Development Facilities and at University at Albany Nanotech Foundation. References [1]Y. Ushiki et al., Proceeding of the VLSI Multilevel Interconnection, (1990) pp. 413 [2] S. P. Jeng et al., Proceeding of Advanced Metallization for Devices and Circuits, (1994) pp. 25. [3] J. R. Lloyd et al., IEEE Transaction on Devices and Materials Reliability, vol. 5, no.1, pp.113-118, March 2005.

Robust ultrathin (20 nm) trilayer low k SiNx/SiNy/SiCNH dielectric Cu caps (k ~4.0-4.2) with post ultraviolet (UV) cure compressive stress were developed and integrated into 22nm CMOS Back End Of Line (BEOL) devices. The new cap reduces device's capacitance (~ 4 %) and enhances stress stability in Cu-Ultra low k structures