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PurposeThe purpose of this paper is to investigate and explain thermal oxide effect on electrochemical corrosion resistance anodized stainless steel (SS).Design/methodology/approachElectrochemical corrosion resistance of thermal oxides produced on anodized 304 SS in air at 350°C, 550°C, 750°C and 950°C in 3.5 wt.% NaCl solution have been investigated by dynamic potential polarization, EIS and double-loop dynamic polarization. Anodized 304 SS were obtained by anodization at the constant density of 1.4 mA.cm-2in the solution containing 28.0 g.L-1H3PO4, 20.0 g.L-1C6H8O7, 200.0 g.L-1H2O2at 70°C for 50 min. SEM and EDS had been also used to characterize the thermal oxides and passive oxide.FindingsInterestingly, anodized 304SS with thermal oxide produced at 350°C displayed more electrochemical corrosion and pitting resistance than anodized 304 SS only with passive oxide, as related to the formation of oxide film with higher chromium to iron ratio. Whereas, anodized 304SS with thermal oxide formed at 950°C shows the worse electrochemical corrosion and pitting resistance among those formed at the high temperatures due to thermal oxide with least compact.Originality/valueWhen thermally oxidized in the range of 350°C–950°C, electrochemical corrosion and pitting corrosion resistance of anodized 304 SS decrease with the increase of temperature due to less compactness, more defects of thermal oxide.

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

This chapter aims at reviewing the characterisation techniques that are commonly used for high temperature oxidation study, especially on stainless steels. In addition, the experimental studies about the high temperature oxidation i.e. thermogravimetric method and chromium volatilisation measurement are explained. The various kinds of characterisation techniques for physico-chemical and electronic properties of thermal oxide scales are reviewed, starting from optical microscopy (OM), scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDS), focused ion beam coupled with scanning electron microscope (FIB/SEM), X-ray diffractometer (XRD), X-ray photoelectron spectroscopy (XPS), Raman spectroscopy (RS), and photoelectrochemical characterisation (PEC). The review focuses on the basic concepts and shows how the characterising tools can be applied to thermal oxide characterisation.

The evolution of different oxidation states during thermal oxidation of (100) oriented Ge substrate was investigated with X-ray photoelectron spectroscopic analysis. The thermally grown oxides in the temperature range of 380 to 500°C were found to consist of four different oxidation states of Ge, namely, Ge1+, Ge2+, Ge3+, and Ge4+. The fractional composition of the oxide species is seen to be dependent on oxidation temperature. Spectroscopic depth profiling reveals variation of oxide composition along the depth of the oxide layer with a large concentration of GeO2 near the oxide surface and a large concentration of suboxides near the oxide/Ge interface. The results obtained in the investigation will help in achieving greater insight into the thermal oxidation process of Ge

The efficacy of implantable medical devices is limited by the longevity of devices in the body environment. Due to the aqueous and mobile-ion rich environment of tissue, robust and long-lasting encapsulation materials are critical for chronic implants. Assessing the reliability of medical devices is commonly performed through saline soak tests with reactive oxidative species at elevated temperatures and lifetime data are fit to an Arrhenius model to predict lifetime under physiological conditions. While effective, these systems often require frequent human involvement to maintain system temperature and reactive oxidative species concentration, as well as monitor sample lifetime, which makes long term testing of multiple samples difficult. Here we present an automated, low-cost, low-solution volume, and high-throughput reactive accelerated aging system to assay many thin film samples in an easy and low maintenance manner. The efficacy of up to 16 thin film coating samples can be assessed by our system through in-situ current leakage tests in a mock biological environment. We validate our system by aging thermal oxide and a-SiC thin films at 93 °C with 20 mM H 2 O 2 . Our system shows early failure of the thermal oxide compared to the a-SiC, in agreement with the current literature.

This paper analyzed the special failure pattern in the wafer center region of 65nm NOR flash. By circuit and failure checking, confirmed the root cause is that the low read current from the big resistance induced by photo residues in self-align-source (SAS) area. The voltage non -uniformity and check-board yield failure were ascribed to the silicon dislocation in SAS active area induced by SAS loop implant. Additional anneal, and higher temperature of rapid thermal oxide, can improve these issue by repairing the dislocation. Decreasing resistance of SAS by dose can also improve yield loss corresponding to erasing cell. All above know-hows helped us to comprehend the new clue and orientation to optimize failure induced by erase failure, and provided the experience for continuous shrinkage of floating NOR flash cell.

We experimentally studied the influence of both impurity density and dangling-bond density on PL emissions from group-IV-semiconductor quantum-dots (IV-QDs) of Si and SiC fabricated by hot-ion implantation technique, to improve the PL intensity (I PL) from IV-QDs embedded in two types of insulators of quartz-glass (QZ) with low impurity density and thermal-oxide (OX) layers. First, we verified the I PL reduction in the IV-QDs in QZ. However, we demonstrated the I PL enhancement of IV-QDs in doped QZ, which is attributable to multiple-level emission owing to acceptor and donor ion implantations into QZ. Secondly, we confirmed the large I PL enhancement of IV-QDs in QZ and OX, owing to forming-gas annealing with H2/N2 mixed gas, which are attributable to the reduction of the dangling-bond density in IV-QDs. Consequently, it is possible to improve the I PL of IV-QDs by increasing impurity density and reducing dangling-bond density.

This study is performed to investigate the temperature sensitivity of SU-8-based triple-arm Mach–Zehnder interferometer (MZI) and straight waveguide. The proposed SU-8 2000-based rib waveguides are fabricated on a silicon wafer with 1.5-μm SiO2 thermal oxide layer. SU-8 layer of desired thickness is spin-coated onto the silicon wafer followed by patterning of the SU-8 waveguides. Temperature sensitivity of both waveguides is evaluated using the same heating source and under the same environmental conditions. Measurement results show that complex triple-arm MZI having different arm lengths offers a less linear sensitivity compared to the simple straight waveguide.

Graphene, an allotrope of carbon, shows ambipolar transfer characteristics with a linear dispersion relation where the conduction and valence band meets at the Dirac point 1. Owing to an absence of bandgap, it is not feasible to use graphene in logic applications though it is possible to use graphene in analog and RF circuits2. Significant efforts towards the growth and transfer of graphene onto arbitrary substrates 3 4 , 5 6 has made it feasible to scale up graphene device fabrication – early focus on single, exfoliated devices has given way to large area, many-device wafers. From a practical standpoint, a lower operating voltage range, minimal unintentional doping of graphene during processing, and excellent device stability at room temperature is required. Most of the earlier graphene based devices were fabricated on thick (90nm or higher) thermal SiO2 substrate as they provide a better optical contrast after transferring graphene. Unfortunately, this attributes to a higher operating voltage in order to modulate the graphene device. In this work, we demonstrate the feasibility of making devices on thin, 10 nm thermal SiO­2 gate dielectric using CVD graphene with minimal shift in the Dirac point and excellent stability during subsequent operation cycles in air at room temperature. The 10nm thermal SiO2 has a breakdown field of ~9.7MV/cm and mobilities as high as 2200 cm2/V·S is achieved in a relatively small operating voltage (±8V). A higher mobility is typically seen for devices located at the center of the transferred graphene region. The 10nm dielectric used in our process is challenging for integration since graphene cannot be visually inspected during device fabrication, but we have overcome this limitation by implementing specialized characterization steps that allow us to monitor the graphene. A lower contact resistivity of 500 Ω-µm and sheet resistance (RSh) of 400Ω/□ is observed at a higher doping level achieved by applying a fixed back gate bias with Ni/Au contact. A similar trend is seen in the RSh extracted from a more appropriate test structure (Van der Pauw), wherein there is a minimal metal contact overlap with graphene. The hysteresis for these graphene devices are consistently less than or equal to 0.3V within the ± 8V sweeping voltage range. Therefore, we demonstrate the fabrication of wafer scale graphene devices with excellent process control on thin dielectric substrate with minimal doping and trapped charge. This could pave way for realization of high performance, low power consuming nanoelectronics with graphene. (1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A. Electric Field Effect in Atomically Thin Carbon Films. Science. 2004, 306, 666–669. (2) Schwierz, F. Graphene Transistors. Nat. Nano. 2010, 5, 487–496. (3) Colombo, L.; Wallace, R. M.; Ruoff, R. S. Graphene Growth and Device Integration. Proc. IEEE 2013, 101, 1536–1556. (4) Banszerus, L.; Schmitz, M.; Engels, S.; Dauber, J.; Oellers, M.; Haupt, F.; Watanabe, K.; Taniguchi, T.; Beschoten, B.; Stampfer, C. Ultrahigh-Mobility Graphene Devices from Chemical Vapor Deposition on Reusable Copper. Sci. Adv. 2015, 1, e1500222(1-6). (5) Kim, H. H.; Lee, S. K.; Lee, S. G.; Lee, E.; Cho, K. Wetting-Assisted Crack- and Wrinkle-Free Transfer of Wafer-Scale Graphene onto Arbitrary Substrates over a Wide Range of Surface Energies. Adv. Funct. Mater. 2016,26, 2070-2077. (6) Li, X.; Cai, W.; An, J.; Kim, S.; Nah, J.; Yang, D.; Piner, R.; Velamakanni, A.; Jung, I.; Tutuc, E.; Banerjee,S. K;Colombo, L.; Ruoff. R. S . Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science . 2009, 324, 1312–1314.

Ag–36.35 wt.% Zn and Ag–38.50 wt.% Zn–0.60 wt.% Al were oxidised in air at 450–650 °C up to 48 h. The oxidation kinetics of both alloys were parabolic with the lower rate constant for the latter alloy. After oxidation for 48 h, thermal oxide scale on Ag–36.35 wt.% Zn was ZnO at all studied temperatures. When 0.60 wt.% Al was added to Ag–38.50 wt.% Zn, ZnO and ZnAl 2 O 4 were formed at all studied temperatures. Al 2 O 3 was evidently observed at 550 and 650 °C. The formation of Al-containing oxides helped reduce the oxidation rate of Ag–38.50 wt.% Zn–0.60 wt.% Al.

We have deposited dense and pinhole-free thin films of SiO2, Al2O3 and ITO at room temperature via ion beam sputtering. The SiO2 films were found to be of similar quality as thermal oxide with a resistivity greater than 1015 Ω·cm and breakdown field in excess of 7 MV/cm. The Al2O3 films were part of a Pt- Al2O3-Pt vertical tunnel junction and were kept extremely thin, from 2 nm to 4 nm. The current-voltage characteristics of these junctions indicated a breakdown field in excess of 20 MV/cm, roughly twice that achieved by ALD films. This breakdown voltage was found to be independent of junction area, strongly suggesting the absence of pinholes in the film. The ITO films were 50 nm to 100 nm thick. As deposited, they are fully transparent with an electrical resistivity of 5x10-4 Ω·cm.

The surface morphology of GaSb was investigated by changing growth conditions such as thermal oxide desorption temperature, growth temperature, and growth step by solid source molecular beam epitaxy. At high temperature growth, the pits caused by the thermal oxide desorption remained in the GaSb buffer layer surface, while the surface was sufficiently flattened. At low temperature growth, the pits disappeared, while the surface was not enough flattened even in the case of step-flow mode growth. Since the pits disappeared at lower growth temperature regardless of the growth mode, this behavior might be explained by the Ga migration length depending on the growth temperature. By applying two-step high/low temperature growth, where both growth steps proceed in step-flow mode, flat, a pit-free GaSb buffer surface could be obtained.

International audience; Carbohydrate microarrays represent powerful tools to study and detect carbohydratebinding proteins, pathogens or cells. In this paper, we report two original oximebased methods to prepare surfaces displaying well-defined structures and valency in a given microspot with improved recognition potency with lectins. In a first “direct” approach, fully synthetic aminooxylated glycoclusters have been coated onto aldehyde-activated SiO$_2$ (silicium substrate doped with 50 nm thermic oxide layer). To improve the preparation of the microarray in term of rapidity and simplicity and to provide addressable surfaces on which sugars can be linked chemoselectively as clusters at defined plots, a second “indirect” strategy has been developed using successive oxime ligation steps. In both cases, binding assays with labelled lectins have revealed more potent and selective interaction due to the clustered presentation of sugars. The observed differences of interaction have been confirmed in solution by ITC.

In this paper, the electrical properties of a thermal oxide (SiO2) grown onto 3C-SiC layers on silicon were investigated, by monitoring the behavior of MOS capacitors. In particular, the growth rate of thermal SiO2 was dependent on the different surface roughness condition. However, independent of the roughness a high density of positive charge was detected. The sample having the smooth surface (subjected to CMP) showed a notably improved dielectric breakdown (BD) field. However, the best BD on macroscopic MOS capacitors was still far from the ideal behavior. Additional insights could be gained employing a nanoscale characterization that revealed the detrimental role of persisting extended defects in the semiconductor. In the semiconductor region far from extended defects the nanoscale BD kinetics was nearly ideal.

(Attention for corrosion science, the abstract must not exceed more than 100 words) In this research, first a multi-analytical approach was carried out to propose a mechanistic model for the formation of the thermal oxide film on low Cr stainless steel. It describes the effects of kinetically and thermodynamically driven phenomena on the growth of a Fe-Cr complex oxide film at 950℃. Second, the behavior of the thermal oxide film in the presence of fluoride ions, as a relevant pickling agent in conversion treatment, was investigated. It was shown that fluoride ions enter the oxide film and form a complex with Fe and preferentially dissolve hematite islands through a complexation mechanism.

This paper reports on the effect of oxidation on fracture behavior of single crystal silicon (SCS). SCS specimens were fabricated from (1 0 0) silicon-on-insulator wafer with 5-μm-thick device layer and oxide layer were thermally grown. Quasi-static tensile testing of as-fabricated, oxidized and oxidized layer removed specimens was performed. The fracture origin location transited from the surface to silicon/oxide interface and inside of silicon. The transition may be caused by surface smoothing, thickening oxide layer and formation of oxide precipitation defects in silicon during oxidation. The radius of the oxide precipitation defects was estimated, which is well agreed with the fracture-initiating crack sizes.

The effects of NO and forming gas post oxidation annealing treatments on the interfacial properties and reliability of thermal oxides grown on n-type 4H-SiC (0001) Si face have been investigated in this study. The results show that forming gas annealing (FGA) treatment has limited effect on interface trap density ( D it ) while it results in an improvement of the insulating properties of thermal oxide with uniform high FN barrier height (2.56 eV), high field-to-breakdown (10.71 MV/cm) and charge-to-breakdown (0.078 C/cm 2 ). On the other hand, NO annealing causes a drastic reduction in D it in the entire energy level, but in the case of reliability, it is not so effective as FGA, with lower barrier height (2.52 eV), field-to-breakdown (10.08 MV/cm), charge-to-breakdown (0.025 C/cm 2 ) and worse uniformity of oxide. The combined NO&FGA treatment was also studied. It leads to a significant reduction in interface trap density further, especially in deep energy level ( E C -E T ≥ 0.4 eV). As for reliability, it brings about uniform barrier height (2.69 eV), field-to-breakdown (10.15 MV/cm) and charge-to-breakdown (0.024 C/cm 2 ). Taking interfacial properties and reliability into account, combined NO&FGA treatment is a promising POA technique for fabrication of high-quality SiC MOS devices.

The impedance behavior of pre-oxidized iron in liquid lead-bismuth eutectic (LBE) at 200 °C is studied using electrochemical impedance spectroscopy. The structures and resistance of oxide grown on iron oxidized in air at different temperatures and durations are compared. The results show that the resistance of the oxide film increases with increasing oxidizing temperature, due to the formation of a thicker scale and fewer defects. At the same temperature (600 °C), increasing the oxidation time can also reduce the defect concentration in the oxide film and improve the impedance of the oxide scale in LBE.

One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2–3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0151509jss] All rights reserved.

International audience; In the present work, mechanical features in thermal oxide films growing on metals have been investigated during cyclic thermal loadings. An adapted model is considered to describe the stress evolution within oxide films, taking into account thermomechanical couplings. These numerical predictions are compared with experimental results obtained using synchrotron diffraction at ESRF. In order to obtain the features of the system, an innovative data treatment is thus proposed and performed. By dealing with the frequency analysis of the system, the method is able to identify some mechanisms. This mechanical spectroscopy allows thus to confirm the thermomechanical description of a chromia-former alloy.

The thickness influence of thermal oxide layers on Si(111) substrates on the formation of self-catalyzed InAs nanowires (NWs) grown by metal-organic chemical vapor deposition (MOCVD) has been investigated. It is found that the thickness of the thermal oxide layer has a strong effect on the morphological characteristics of InAs NWs formed on the Si substrates. In particular, within a suitable thickness range, it is possible to achieve vertical InAs NWs with a uniform distribution of their positions, lengths and diameters. In addition, growth on the thermal oxide layer both improves the morphology of the NWs, and suppresses the frequently observed parasitic islands compared to growth on bare Si. A growth model, which is based on the diffusion length of adatoms, the growth temperature, the thickness of thermal oxide layer, the size and the density of thermal oxide holes, has been developed to explain the formation of the self-catalyzed InAs NWs on the Si substrate with a thermal oxide layer.

The conduction mechanism of the leakage current in thermal oxide on 4H-SiC was identified. The carrier separation current-voltage method clarified that electrons are the dominant carriers of the leakage current. The temperature dependence of the currentvoltage characteristics indicated that the conduction mechanism of the leakage current involved not only Fowler-Nordheim tunneling (FN) but also Poole-Frenkel (PF) emission. The PF emission current due to the existence of defects in the oxide increased with temperature.