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Edge computing, which has been gaining attention in re-cent years, has many advantages, such as reducing the load on the cloud, not being affected by the communication environment, and providing excellent security. Therefore, many researchers have attempted to implement neural networks, which are representative of machine learning in edge computing. Neural networks can be divided into inference and learning parts; however, there has been little research on implementing the learning component in edge computing in contrast to the inference part. This is because learning requires more memory and computation than inference, easily exceeding the limit of resources available for edge computing. To overcome this prob-lem, this research focuses on the optimizer, which is the heart of learning. In this paper, we introduce our new optimizer, hardware-oriented logarith-mic momentum estimation (Holmes), which incorporates new perspectives not found in existing optimizers in terms of characteristics and strengths of hardware. The performance of Holmes was evaluated by comparing it with other optimizers with respect to learning progress and convergence speed. Important aspects of hardware implementation, such as memory and oper-ation requirements are also discussed. The results show that Holmes is a good match for edge computing with relatively low resource requirements and fast learning convergence. Holmes will help create an era in which advanced machine learning can be realized on edge computing.

The rising demand for high quality display has ensued active research in high dynamic range (HDR) imaging, which has the potential to replace the standard dynamic range imaging. This is due to HDR’s features like accurate reproducibility of a scene with its entire spectrum of visible lighting and color depth. But this capability comes with expensive capture, display, storage and distribution resource requirements. Also, display of HDR images/video content on an ordinary display device with limited dynamic range requires some form of adaptation. Many adaptation algorithms, widely known as tone mapping (TM) operators, have been studied and proposed in the last few decades. In this paper, we present a comprehensive survey of 60 TM algorithms that have been implemented on hardware for acceleration and real-time performance. In this state-of-the-art survey, we will discuss those TM algorithms which have been implemented on GPU [1]–[12], FPGA [13]–[47], and ASIC [48]–[60] in terms of their hardware specifications and performance. Output image quality is an important metric for TM algorithms. From our literature survey we found that, various objective quality metrics have been used to demonstrate the quality of those algorithms hardware implementation. We have compiled those metrics used in this survey [61], [62], and analyzed the relationship between hardware cost, image quality and computational efficiency. Currently, machine learning-based (ML) algorithms have become an important tool to solve many image processing tasks, and this paper concludes with a discussion on the future research directions to realize ML-based TM operators on hardware.

Reservoir computing (RC) is possible using physical systems. We have previously proposed an RC for ideal atomic switches. When temporal current fluctuations (noise) from the measurement of actual atomic switches are introduced into the proposed RC, performance degrades significantly. To address this issue, we propose novel methods for increasing the operating current range and observing the atomic switch several times to determine the average noise. Consequently, the memory capacity of the RC model increased, despite the presence of noise. To improve the precision of RC, we investigated the capacity and showed that changing the time constant of atomic switches results in an improvement.

Reducing the number of connections in hardware artificial neural networks, as compared with their software counterparts, can result in a drastic reduction in costs, because the reduction translates into utilizing fewer devices. This paper presents the demonstration of a method, by using simulations, to halve the amount of weights in a network while minimizing the accuracy loss. Additionally, the appropriate considerations for translating these simulation results to hardware networks are also detailed.

Stochastic Computing (SC) [2] is a probability-based computing method, which enables the performance of various operations with a small number of logic gates (i.e., low power) in exchange for high accuracy. Using SC for edge artificial intelligence (AI) integrated circuits can help circumvent the limitations inherent in the power and area required for edge AI. In this study, a three-layered Neural Network (NN) is presented with an online learning function that introduces pseudo-activation, pseudo-subtraction, and imperfect addition into the SC framework. This method may expand the options for edge AI integrated circuits using SC.