1,098 results on '"Test vector"'
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2. Mass Storage Chip Design Case
3. Galois self-dual cuspidal types and Asai local factors.
4. Introduction
5. Critique on Signature Analysis Using Cellular Automata and Linear Feedback Shift Register
6. Testing, Yield, Packaging, Debug and Failure Analysis
7. Delay Testing Based on Multiple Faulty Behaviors
8. A Novel Sparsity Based Classification Framework to Exploit Clusters in Data
9. Assisted Coverage Closure
10. Boundary-Scan Testing
11. Principles and Applications of Polymorphic Circuits
12. Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability
13. FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction
14. The Spectral Structure of a Nonlinear Operator and Its Approximation
15. Automated Debugging for Timing Variations
16. A new test vector optimization method for failure isolation
17. Concurrent Learning Algorithm and the Importance Map
18. Using BLAKE
19. Back-To-Back Testing of Model-Based Code Generators
20. True Error or False Alarm? Refining Astrée’s Abstract Interpretation Results by Embedded Tester’s Automatic Model-Based Testing
21. Chapter 22 Week 11 Class 1
22. The Locally Corrected Nyström Method for Electromagnetics
23. NoC Verification and Testing
24. Low Cost C-Testable Finite Field Multiplier Architectures
25. Signature-Based Reliability Analysis
26. Testing Logic Circuits for Probabilistic Faults
27. Custom Winding Ratio Analysis of Evolutionary Optimized Audio Transformer
28. On the Origin of Yet another Channel
29. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures
30. ML Confidential: Machine Learning on Encrypted Data
31. Functional Test Compaction
32. Accelerating Processor Verification Based on ESL Model
33. Modeling and Testing of Automation Systems
34. Simulink-Hardware Flow
35. Wordlength Optimization
36. A Process Algebra Based Strategy for Generating Test Vectors from SCR Specifications
37. NoC Reuse for SoC Modular Testing
38. Protecting IPs Against Scan-Based Side-Channel Attacks
39. Hardware Metering: A Survey
40. Background on VLSI Testing
41. Hardware Trojan Detection
42. On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization
43. Fuzzing: Cyberphysical System Testing for Security and Dependability
44. 13 Evolutionary Test Generation Methods for Digital Devices
45. Dynamic Ensemble Selection for Off-Line Signature Verification
46. Circuit Design with Resonant Tunneling Diodes
47. Logic Built-in Self-test
48. Design for Test by Means of Scan
49. Deterministic Test Generation Algorithms
50. Fault Simulation Applications and Methods
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