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A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.

We present the GroundHog 2009 benchmarking suite that evaluates the power consumption of reconfigurable technology for applications targeting the mobile computing domain. This benchmark suite includes seven designs; one design targets fine-grained FPGA fabrics allowing for quick state-of-the-art evaluation, and six designs are specified at a high level allowing them to target a range of existing and future reconfigurable technologies. Each of the six designs can be stimulated with the help of synthetically generated input stimuli created by an open-source tool included in the downloadable suite. Another tool is included to help verify the correctness of each implemented design. To demonstrate the potential of this benchmark suite, we evaluate the power consumption of two modern industrial FPGAs targeting the mobile domain. Also, we show how an academic FPGA framework, VPR 5.0, that has been updated for power estimates can be used to estimates the power consumption of different FPGA architectures and an open-source CAD flow mapping to these architectures.

The list of significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced theory and practice in the field.

This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.

Handheld mobile terminals have developed from simple phones to devices featuring a wide variety of modern multimedia functions, being in fact multimedia computers. In today's mobile terminals, computational demand is closes to that of personal desktop computers only a few years ago. All these new features need more power and bandwidth in interconnections. New innovations must be implemented in these devices with ever increasing speed.The MIPI, Mobile Industry Processor Interface, standardization forum is tackling these challenges by standardizing the interfaces used in mobile terminals. Some of the advances this forum is working on are:• The serialization of interfaces which aims to reduce the pincount in ICs,• New physical layer designs which are optimized for per bit energy consumption,• Universally applicable protocols that can be widely used while they are not specified for a certain application only, thus giving flexibility to the design of devicesWith standard interfaces, companies no longer need to spend time in new projects on designing interfaces for different customers. They can thus release those resources for other design work. They can also obtain a wider potential customer base. Also customers can free their resources from interface design, when the standardization work is done. Customers can enjoy choosing from a larger potential supply base and their time to market with new innovative products is increased considerably. Nokia sees standard interfaces as a critical enabler for pincount and power efficient designs and getting new innovations and applications to the market considerably faster.

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

This paper presents development of a SoftSONIC virtual hardware platform for lossless high-resolution real-time JPEG 2000 encoding applications. It is demonstrated how a SystemC transaction level model of the platform can be used for automated architecture design exploration in three imaging application domains: medical, typical, and worst-case imaging. It is shown that with the virtual hardware platform it is possible to determine whether an architecture can sustain real-time processing requirements or not over 240 times faster than with RTL VHDL simulation. The virtual platform gives feedback of the design choices in memory and hardware resource usage and clock frequency requirements. These cannot be obtained from algorithmic C/C++ or Matlab model. In addition, by using a simple procedure to increase the parallelism of the system, our approach enables automated generation of customised architecture for varying processing requirements.

This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity transaction level modelling (TLM) and clocked register transfer level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder

This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. The solution is based on network of Nodes, communicating using packet-based protocol. The approach is illustrated using SoftSONIC, a CMP for video applications. Our approach promotes modularity and design reuse by having multiple interoperable layers of design abstraction, while supporting advanced development and verification methods such as mixed-abstraction execution and efficient system-level simulation based on Transaction Level Modelling. The platform provides domain-specific abstractions and customisations of various elements such as communication protocols and topology, enabling exploitation of data locality and fine- and coarse-grain parallelism. The benefits of our approach is demonstrated using SoftSONIC for development of several real-time HDTV video processing applications.

This paper presents a technique for realizing adaptive FIR filters that use constant-coefficient multipliers on a run-time reconfigurable FPGA. Three different adaptive FIR filter architectures for run-time reconfigurable FPGAs are presented. It is shown that run-time reconfigurable logic can be used to efficiently implement adaptive constant-coefficient FIR filters. With reasonable configuration latency, benefits in speed, area and power consumption are obtained.

This paper presents a system-level approach for modelling and implementing hardware-software systems, which contain Run-Time Reconfigurable (RTR) hardware. The developed technique provides management and scheduling of RTR tasks from system-level simulations to synthesizable VHDL descriptions. The developed technique was implemented using OCAPI-xl - a system-level modelling and implementation tool based on C + + libraries. The proposed approach allows designers to explore the tradeoffs between implementation of system partitions in software, static hardware, and RTR hardware. After the system has been partitioned, an OCAPI-xl-based design flow can be utilized for implementation of all the system components.

This paper presents the architecture and the implementation of a novel general-purpose prototyping platform for dynamically reconfigurable designs. Using dynamical reconfigurability the hardware can be reused even inside the data flow processing. This extends the capabilities of the hardware significantly. The presented platform enables rapid prototyping and verification of dynamic reconfiguration in large variety of designs in various applications. Due to its Linux-based operating system and versatile debugging and I/O capabilities, design time and effort to operate with the platform can be minimized. In this platform, dynamic reconfiguration is based on Atmel AT40K-series FPGA. The platform is the first one utilizing this FPGA architecture's abilities in dynamic reconfiguration.

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