431 results on '"Temes, G.C."'
Search Results
2. High‐linearity SAR‐VCO MASH ΔΣ ADC with second‐order noise shaping
3. Noise‐shaped filter implementation
4. Wide‐band high‐accuracy ΔΣ ADC using segmented DAC with DWA and mismatch shaping
5. Power efficient noise‐coupled ΔΣ ADC with simple delay cells
6. Fully passive third‐order noise shaping SAR ADC
7. Passive switched‐capacitor filter with complex poles for high‐speed applications
8. Multi‐step incremental ADC with extended binary counting
9. Double‐sampled wideband delta–sigma ADCs with shifted loop delays
10. Efficient technique for excess loop delay compensation in continuous‐time ΔΣ modulators
11. Two‐step incremental analogue‐to‐digital converter
12. Multi‐step extended‐counting analogue‐to‐digital converters
13. Accuracy‐enhanced switched‐capacitor stages using low‐gain opamps
14. Noise‐shaping SAR ADC using three capacitors
15. Charge compensation technique for switched-capacitor circuits
16. Teraohm on-chip resistance realisation using switched capacitor topologies
17. Digital DAC calibration technique for and incremental modulators
18. Double noise coupling analogue-to-digital converter
19. High-precision switched-capacitor integrator using low-gain opamp
20. Low-power and low-offset comparator using latch load
21. Comparator-based buffer with resistive error correction
22. Two-step split-junction SAR ADC
23. Switched-R tuning technique for Gm-C filters
24. Low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs
25. Multi-step capacitor-splitting SAR ADC
26. Power-up calibration techniques for double-sampling modulators
27. Noise-coupled continuous-time delta-sigma ADCs
28. Improved architecture for low-distortion ADCs
29. Noise-shaped integrating quantisers in modulators
30. Double-sampled modulator with relaxed feedback timing
31. Single-loop modulator with extended dynamic range
32. Mixed-Order Sturdy MASH Δ-Σ Modulator
33. Dynamic biasing scheme for high-speed∕ low-power switched-capacitor stages
34. Efficient floating double-sampling integrator for ADCs
35. A Low-Power 22-bit Incremental ADC
36. Sturdy MASH - modulator
37. Split-set data weighted averaging
38. Correlated double sampling technique for continuous-time filters
39. Noise-coupled ADCs
40. Enhanced split-architecture - ADC
41. Design-oriented estimation of thermal noise in switched-capacitor circuits
42. Stochastic analog-to-digital conversion
43. Theory and Applications of Incremental<tex>$Delta Sigma $</tex>Converters
44. An Efficient>tex<$Delta Sigma $>/tex
45. Simple and efficient noise estimation algorithm
46. A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application.
47. A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW.
48. 82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction.
49. A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer.
50. Low-power switched-capacitor integrator for delta-sigma ADCs.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.