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In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocations in ZnSSe/GaAs (001) heterostructures, with applications to dislocation sidewall gettering (DSG) in devices. Current modeling approaches are based on the extension of the original Dodson and Tsao plastic flow model [B. W. Dodson and J. Y. Tsao, Appl. Phys. Lett., 51, 1325 (1987); Appl. Phys. Lett., 52, 852 (1988)] to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent breakthroughs have greatly enhanced the utility of these modeling approaches in three respects: i) pinning interactions have been included in graded and multilayered structures, providing a better description of the rate of strain relaxation as well as the limiting value; ii) a refined model describing the interaction length for dislocation-dislocation interactions was formulated to include jogging in compositionally-graded and step-graded layers; and iii) inclusion of back-and-forth weaving of dislocations provides a more accurate description of heterostructures containing strain reversals, such as strained-layer superlattices or overshoot graded layers. We will describe these three key advances and use reasonable estimates of the kinetic parameters for ZnSSe to explain and illustrate practical features of dislocation sidewall gettering in II-VI heterostructures.

Plastic flow models for lattice relaxation in II–VI heterostructures have increased in sophistication, including thermal strains as well as dislocation multiplication, annihilation, coalescence, and compensation. However, despite evidence for the importance of pinning interactions, existing plastic flow models have not accounted for these interactions, whereby a gliding threading dislocation associated with a misfit dislocation along a type direction is impeded by interaction with a misfit dislocation along the orthogonal type direction. Such an impediment to glide will tend to reduce the extent of strain relaxation, perhaps appreciably in layers which are thin or exhibit low residual strain; in these cases, the motion of a gliding dislocation could be arrested altogether. In this paper we present a practical model for pinning interactions which can be used to extend the usefulness of plastic flow models, and we compare this model against experimental results for ZnSySe1y/GaAs (001) heterostructures.

It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnSySe1-y/GaAs (001) relative to ZnSe/GaAs (001).

Dislocation sidewall gettering (DSG) is an important method for the removal of device-compromising defects from optoelectronic devices such as detectors and light-emitting diodes. DSG involves the patterned epitaxy or post-growth patterning and annealing, and allows misfit dislocations to elongate until they are captured by image forces at sidewalls. Despite this physical understanding of the process, practical application of DSG has often been guided by empirical studies due to the scarcity of modeling studies. In this work we apply a detailed model for lattice relaxation and dislocation dynamics to DSG in heteroepitaxial ZnSSe/GaAs (001), considering the effects of thickness, composition, growth temperature, and annealing, and we compare modeling and experimental results for this material system.

Metamorphic semiconductor devices often contain abrupt mismatched interfaces with relatively high densities of misfit dislocations. In such cases there has been some experimental evidence for pinning interactions, whereby a gliding threading dislocation associated with a misfit dislocation along a type direction is impeded by interaction with a misfit dislocation along the orthogonal type direction. This impediment to glide will tend to reduce the extent of strain relaxation, and this effect is expected to be significant in thin layers for which the impediment is sufficient to arrest the motion of the gliding dislocation altogether. In this paper we present a practical model for pinning interactions which can be used to extend the usefulness of plastic flow models down to the pseudomorphic limit, and we compare this model against experimental results for InGaAs/GaAs (001) heterostructures.

In order to evaluate various buffer layers for metamorphic devices, threading dislocation densities have been calculated for uniform composition In x Ga1−xAs device layers deposited on GaAs (001) substrates with an intermediate graded buffer layer using the LMD model, where LMD is the average length of misfit dislocations. On this basis, we compare the relative effectiveness of buffer layers with linear, exponential, and S-graded compositional profiles. In the case of a 2 μm thick buffer layer linear grading results in higher threading dislocation densities in the device layer compared to either exponential or S-grading. When exponential grading is used, lower threading dislocation densities are obtained with a smaller length constant. In the S-graded case, lower threading dislocation densities result when a smaller standard deviation parameter is used. As the buffer layer thickness is decreased from 2 μm to 0.1 μm all of the above effects are diminished, and the absolute threading dislocation densities increase.

In this talk we will describe state-of-the-art approaches to the modeling of strain relaxation and dislocations in ZnSySe1-y/GaAs (001) heterostructures, with applications to dislocation sidewall gettering (DSG) in devices. Current modeling approaches are based on the extension of the original Dodson and Tsao plastic flow model [B. W. Dodson and J. Y. Tsao, Appl. Phys. Lett., 51, 1325 (1987); Appl. Phys. Lett., 52, 852 (1988)] to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent breakthroughs have greatly enhanced the utility of these modeling approaches in three respects: i) pinning interactions have been included in graded and multilayered structures, providing a better description of the rate of strain relaxation as well as the limiting strain; ii) a refined model describing the interaction length for dislocation-dislocation interactions was formulated to include jogging in compositionally-graded and step-graded layers; and iii) inclusion of back-and-forth weaving of dislocations provides a more accurate description of heterostructures containing strain reversals, such as strained-layer superlattices or overshoot graded layers. We will describe these three key advances and use reasonable estimates of the kinetic parameters for ZnSySe1-y to explain and illustrate practical features of dislocation sidewall gettering in II-VI heterostructures.

The design and analysis of semiconductor strained-layer device structures require an understanding of the equilibrium profiles of strain and dislocations associated with mismatched epitaxy. Although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be found numerically by energy minimization using an appropriate partitioning of the structure into sublayers, such an approach is computationally intense and non-intuitive. We have therefore developed a simple electric circuit model approach for the equilibrium analysis of these structures. In it, each sublayer of an epitaxial stack may be represented by an analogous circuit configuration involving an independent current source, a resistor, an independent voltage source, and an ideal diode. A multilayered structure may be built up by the connection of the appropriate number of these building blocks, and the node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits can easily be extended to the relaxation of strained-layer structures. Furthermore, the electrical circuit model may be extended to continuously-graded epitaxial layers by considering the limit as the individual sublayer thicknesses are diminished to zero. In this paper, we describe the mathematical foundation of the electrical circuit model, demonstrate its application to several representative structures involving In x Ga1−x As strained layers on GaAs (001) substrates, and develop its extension to continuously-graded layers. This extension allows the development of analytical expressions for the strain, misfit dislocation density, critical layer thickness and widths of misfit dislocation free zones for a continuously-graded layer having an arbitrary compositional profile. It is similar to the transition from circuit theory, using lumped circuit elements, to electromagnetics, using distributed electrical quantities. We show this development using first principles, but, in a more general sense, Maxwell’s equations of electromagnetics could be applied.

The design of heterostructures that exhibit desired strain characteristics is critical for the realization of semiconductor devices with improved performance and reliability. The control of strain and dislocation dynamics requires an understanding of the relaxation processes associated with mismatched epitaxy, and the starting point for this analysis is the equilibrium strain profile, because the difference between the actual strain and the equilibrium value determines the driving force for dislocation glide and relaxation. Previously, we developed an electrical circuit model approach for the equilibrium analysis of semiconductor heterostructures, in which an epitaxial layer may be represented by a stack of subcircuits, each of which involves an independent current source, a resistor, an independent voltage source, and an ideal diode. In this work, we have applied the electrical circuit model to study the strain compensation mechanism and show that, for a given compositionally uniform device layer with fixed mismatch and layer thickness, a buffer layer may be designed (in terms of thickness and mismatch) to tailor the strain in the device layer. A special case is that in which the device layer will exhibit zero residual strain in equilibrium (complete strain compensation). In addition, the application of the electrical circuit analogy enables the determination of exact expressions for the residual strain characteristics of both the buffer and device layers in the general case where the device layer may exhibit partial strain compensation. On the basis of this framework, it is possible to develop design equations for the tailoring of the strain in a device layer grown on a uniform composition buffer.

We have investigated the evolution of the strain and threading dislocation density in metamorphic compositionally and temperature-graded ZnSySe1−y buffer layers. Linear variation in composition in conjunction with temperature grading may allow control over the relaxation process. Previously, we reported the development of a general kinetic model based on dislocation flow, which accounted for the time evolution of the strain relaxation in semiconductor structures under kinetically limited conditions, including interactions of threading and misfit defects. In this work, we studied ZnSySe1−y/GaAs (001) heterostructures with linear compositional grading and a convex-upward (type A), linear (type B) or convex-downward (type C) temperature grading profile. The thermal budget available for relaxation in these types of structures is controlled by the temperature grading profile, made up of combinations of linear ramps and constant-temperature sections. In all cases, the temperature was varied from T0 (400°C to 600°C) at the substrate interface to TF = 300°C at the surface. We also investigated the effect of varying the compositional gradient in the range from 0.18%/μm to 1.6%/μm. Structures with higher average temperature (greater thermal budget) and/or higher grading coefficient exhibited greater extent of relaxation and therefore reduced residual strain. Furthermore, controlling the extent of strain relaxation enabled optimization of the dislocation densities in these heterostructures.

The inclusion of metamorphic buffer layers (MBLs) in the design of lattice-mismatched semiconductor heterostructures is important in enhancing reliability and performance of optoelectronic and electronic devices through proper control of threading dislocations; threading dislocation can be reduced by allowing the distribution of the misfit dislocations throughout the MBL, rather than concentrating them at the interface where substrate defects and tangling can pin dislocations or otherwise reduce their mobility. Compositionally graded layers have been particularly used for this purpose and in this work we considered heterostructures involving a step-graded InxGa1−xAs or InxAl1−xAs epitaxial layer on a GaAs (001) substrate. For each structure type, we present minimum energy calculations including (i) the surface and (ii) average in-plane strain and (iii) the misfit dislocation density profile with various grading coefficients (thickness and indium composition variation). In both types of structures, the average in-plane strain and misfit dislocation density profile scale with the average grading coefficient, but InxAl1−xAs structures with a greater average elastic stiffness constants exhibit slightly higher average compressive in-plane strain (absolute valued) which is associated with higher misfit dislocation densities. However, the rate of change in the normalized relaxation percentage per unit thickness of each step with respect to the lattice mismatch of the step is lower in the InxAl1−xAs material system. The difference of the in-plane strain is small (

Strained-layer superlattices (SLSs) have been used extensively to modify the threading dislocation behavior in metamorphic semiconductor device structures, and have even been utilized as “dislocation filters.” However, up to the present time the application of SLSs in metamorphic structures has been impeded by the lack of detailed physical models for their behavior. In this work we apply a “weaving and jogging” model for dislocation interactions in ZnSSe SLSs to study their expected behavior and the dependence on the SLS design (placement, compositions, thicknesses, and growth conditions). Based on this study we make recommendations for the use of SLSs in the modification of threading dislocation behavior in ZnSSe/GaAs (001) device structures.

In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocation dynamics in ZnSSe/GaAs (001) heterostructures. These are based on the extension of the Dodson and Tsao plastic flow model [B. W. Dodson and J. Y. Tsao, Appl. Phys. Lett., 51, 1325 (1987); Appl. Phys. Lett., 52, 852 (1988)] to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent breakthroughs have greatly enhanced the capability of the modeling approach in three respects: i) pinning interactions have been included in graded and multilayered structures for the first time, providing a better description of the limiting strain relaxation as well as the dislocation sidewall gettering; ii) a refined model for dislocation-dislocation interactions including jogging provides a more accurate physical description of compositionally-graded layers and step-graded layers; and iii) inclusion of back-and-forth weaving of dislocations provides a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices and overshoot graded layers. Here we describe these three key advances and illustrate applications of each to practical heterostructures.

Compositional grading is commonly used to accommodate the lattice mismatch in metamorphic semiconductor device structures. Although linearly-graded or linear step-graded approaches are commonly used, there are experimental and theoretical grounds for the expectation that nonlinearly-graded buffer layers could offer advantages in the control of dislocations or strain. In this work we have conducted a detailed modeling study of nonlinearly-graded buffer layers in ZnSSe/GaAs (001) heterostructures to better understand the dislocation dynamics and defect behavior in such nonlinear buffers, and we make comparisons to the well-known case of linear grading.

Strained-layer superlattices (SLSs) have been used to modify the threading dislocation behavior in metamorphic semiconductor device structures; in some cases they have even been used to block the propagation of threading dislocations and are referred to in these applications as “dislocation filters.” However, such applications of SLSs have been impeded by the lack of detailed physical models. Here we present a “zagging and weaving” model for dislocation interactions in multilayers and strained-layer superlattices, and we demonstrate the use of this model to the threading dislocation dynamics in InGaAs/GaAs (001) structures containing SLSs.

Since the invention of dislocation sidewall gettering (DSG) in 2000 the technique has been applied extensively in infrared focal-plane arrays and flat-panel displays. However, development of DSG technology has been guided mostly by empirical trials due to the lack of detailed physical models. Here we demonstrate the application of a dislocation dynamics model to evaluate DSG approaches in both ZnSySe1-y/GaAs (001) and InGaxAs1-x/GaAs (001) heterostructures. We find that the effectiveness of DSG is strongly dependent on composition in both material systems.

Metamorphic semiconductor devices often utilize compositionally-graded buffer layers for the accommodation of the lattice mismatch with controlled threading dislocation density and residual strain. Linear or step-graded buffers have been used extensively in these applications, but there are indications that sublinear, superlinear, S-graded, or overshoot graded structures could offer advantages in the control of defect densities. In this work we compare linear, step-graded, and nonlinear grading approaches in terms of the resulting strain and dislocations density profiles using a state-of-the-art model for strain relaxation and dislocation dynamics. We find that sublinear grading results in lower surface dislocation densities than either linear or superlinear grading approaches.

In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocation dynamics in InGaAs/GaAs (001) heterostructures. Current approaches are all based on the extension of the original Dodson and Tsao plastic flow model to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent break-throughs have greatly enhanced the utility of these modeling approaches in four respects: i) pinning interactions are included in graded and multilayered structures, providing a better description of the limiting strain relaxation as well as the dislocation sidewall gettering; ii) a refined model for dislocation-dislocation interactions including zagging enables a more accurate physical description of compositionally-graded layers and step-graded layers; iii) inclusion of back-and-forth weaving of dislocations provides a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices or overshoot graded layers; and iv) the compositional dependence of the model kinetic parameters has been elucidated for the InGaAs material system, allowing more accurate modeling of heterostructures with wide variations in composition. We will describe these four key advances and illustrate their applications to heterostructures of practical interest.

We have investigated the evolution of strain and threading dislocation density in metamorphic temperature-graded ZnSe buffer layers. Mismatched semiconductor heterostructures may be designed to take advantage of temperature grading to allow control over the relaxation process. To study temperature grading, we have applied a plastic flow model which predicts nonequilibrium strain relaxation as well as misfit and threading dislocation densities by accounting for the time evolution of kinetically limited and equilibrium strain relaxation, thermal activation of glide, and misfit–threading dislocation interactions. We considered ZnSe/GaAs (001) heterostructures comprising a convex-down (type A), linear (type B), and convex-up (type C) temperature grading profile. The thermal budget available for relaxation in these types of structures is controlled by the temperature grading profile, which consists of combinations of linear ramp-down and/or constant temperature growth; the temperature is varied from T 0 (400°C to 600°C) at the substrate interface to T F = 300°C at the surface. We show that structures with a higher thermal budget exhibit a greater extent of relaxation (lower strains). At lower thicknesses, the dislocation density is dominated by the extent of relaxation, whereas at greater thicknesses, it is controlled by annihilation and coalescence mechanisms.

We have investigated the residual in-plane strain and width of the surface misfit dislocation free zone in linearly-graded GaAs1-yPy metamorphic buffer layers as approximated by a finite number of sublayers. For this purpose we have developed an electric circuit model approach for the equilibrium analysis of these structures, in which each sublayer may be represented by an analogous configuration involving a current source, a resistor, a voltage source, and an ideal diode. The resulting node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. Utilizing this new approach, we show that the residual surface strain in linearly-graded epitaxial structures increases monotonically with grading coefficient as well as the number of sublayers, and is strongly dependent on the width of the misfit dislocation free zone, which diminishes with an increasing grading coefficient.

The design of metamorphic buffer layers for semiconductor devices with reduced defect densities requires control of lattice relaxation and dislocation dynamics. Graded layers are beneficial for the design of these buffers because they reduce the threading dislocation density by (1) allowing the distribution of the misfit dislocations throughout the buffer layer therefore reducing pinning interactions, and (2) enhancing mobility from the high built-in surface strain which helps to sweep out threading arms. In this work, we considered heterostructures involving a linearly-graded (type A) or step-graded (type B) buffer grown on a GaAs (001) substrate. For each structure type, we studied the equilibrium configuration and the kinetically-limited lattice relaxation and non-equilibrium threading dislocations by utilizing a dislocation dynamics model. In this work, we have also considered heterostructures involving a constant composition ZnS y Se1−y device layer grown on top of a GaAs (001) substrate with an intermediate buffer layer of linearly-graded (type C) or step-graded (type D) ZnS y Se1−y . For each structure type, we studied the requirements on the thickness and compositional profile in the buffer layer for the elimination of all mobile threading dislocations from the device layer by the dislocation compensation mechanism.

We conducted a modeling study of the threading dislocation behavior in chirped and unchirped InGaAs/GaAs (001) strained-layer superlattices (SLSs) using a Dodson & Tsao / Kujofsa & Ayers (DTKA) type plastic flow model. Four types of SLSs were investigated: type I was chirped using compositional modulation, type II was chirped using layer thickness modulation, type III was unchirped with alternating layers of InGaAs and GaAs, and type IV was unchirped with alternating layers of InGaAs having two different compositions. Generally the surface and average values of the dislocation density decreased with increasing total thickness. The dependence on top indium composition was more complex, due to dislocation compensation and multiplication effects, but for type II and IV superlattices, the average and surface threading dislocation densities increased in nearly monotonic fashion with top indium composition. Based on these results, the compositionally-modulated chirped (type I) and InGaAs/GaAs unchirped (type III) superlattices appear to be best suited as buffer layers for metamorphic devices, while the chirped superlattices with layer thickness modulation (type II) and InGaAs/InGaAs unchirped (type IV) superlattices appear to be poorly suited for use as buffer layers for devices containing high indium content.

There have been a number of studies of dislocation filtering by strained-layer superlattices incorporated into semiconductor heterostructures. Despite the extensive nature of this body of work, a general understanding of the phenomenon has proved elusive, preventing wide application of SLS dislocation filters in practical devices. However, recent advances in the understanding of dislocation dynamics and the consequent development of detailed plastic flow models allow the prediction of threading dislocation density profiles in general semiconductor heterostructures. In this work, we have applied such a plastic flow model to InGaAs/GaAs (001) heterostructures containing an InGaAs-based SLS, and we have studied the dependence of the surface and average threading dislocation densities on the placement and design of the SLS.

Semiconductor device structures are often grown metamorphically on lattice-mismatched substrates using an intermediate buffer layer to accommodate the lattice mismatch and reduce the threading dislocation density. These structures have traditionally been designed empirically but this may not yield the optimum structure in terms of dislocation density reduction. Recently advancements in the understanding of dislocation dynamics have made it possible in principle to design the buffer layer and device structure so that all glissile threading dislocations in the buffer layer are diverted at the interface for the creation of misfit dislocations. In this paper we present a criterion for the complete removal of threading dislocations from the surface of a device structure on a buffer layer, and we discuss its practical application.

The understanding of lattice relaxation and dislocation dynamics in lattice-mismatched semiconductors makes it possible to design metamorphic device structures utilizing the dislocation compensation mechanism for reduced defects, improved performance, and enhanced reliability. We have developed a dislocation dynamics model accounting for misfit–threading interactions and have applied it to ZnSySe1−y/GaAs (001) heterostructures.1 Dislocation compensation involves the removal of threading dislocations associated with one sense of misfit dislocations by bending them over to create misfit dislocations of the opposite sense at an intentionally mismatched interface. Here we investigated the design of dislocation-compensated ZnSySe1−y/GaAs (001) heterostructures and considered the sulfur mole fraction tolerances applicable to such structures. We considered two types of structures: type A involved a uniform-composition (ungraded) layer on top of a uniform-composition buffer, while type B involved a uniform-composition layer on a linearly graded buffer. For each structure type we studied the requirements on the thickness and compositional profile of the buffer layer to optimize the removal of mobile threading dislocations from the top uniform (device) layer as well as the allowed tolerance in compositional overshoot to achieve structures with low threading dislocation density. We show for both types of structure that (i) for given compositional overshoot at the buffer–device layer interface, there is an optimum buffer thickness which minimizes the dislocation density; and (ii) for given buffer thickness there is an optimum overshoot which minimizes the dislocation density.

We present design equations for error function (or “S-graded”) graded buffers for use in accommodating lattice mismatch of heteroepitaxial semiconductor devices. In an S-graded metamorphic buffer layer the composition and lattice mismatch profiles follow a normal cumulative distribution function. Minimum-energy calculations suggest that the S-graded profile may be beneficial for control of defect densities in lattice-mismatched devices because they have several characteristics which enhance the mobility and glide velocities of dislocations, thereby promoting long misfit segments with relatively few threading arms. First, there is a misfit-dislocation-free zone (MDFZ) adjacent to the interface, which avoids dislocation pinning defects associated with substrate defects. Second, there is another MDFZ near the surface, which reduces pinning interactions near the device layer which will be grown on top. Third, there is a large built-in strain in the top MDFZ, which enhances the glide of dislocations to sweep out threading arms. In this paper we present approximate design equations for the widths of the MDFZs, the built-in strain, and the peak misfit dislocation density for a general S-graded semiconductor with diamond or zincblende crystal structure and (001) orientation, and show that these design equations are in fair agreement with detailed numerical energy-minimization calculations for ZnSySe1−y/GaAs (001) heterostructures.

The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled modeling of uniform layers but not the threading dislocations in device structures with arbitrary compositional grading. In this work we present a kinetic model for lattice relaxation which includes misfit–threading dislocation interactions, which have not been considered in previous annihilation–coalescence models. Inclusion of these dislocation interactions makes the kinetic model applicable to compositionally graded structures, and we have applied it to ZnSe/GaAs (001) and ZnSySe1−y/GaAs (001) heterostructures. The results of the kinetic model are consistent with the observed threading dislocation behavior in ZnSe/GaAs (001) uniform layers, and for graded ZnSySe1−y/GaAs (001) heterostructures the kinetic model predicts that the threading dislocation density may be reduced by the inclusion of grading buffer layers employing compositional overshoot. This “dislocation compensation” effect is consistent with our high-resolution x-ray diffraction experimental results for graded ZnSySe1−y/GaAs (001) structures grown by photoassisted metalorganic vapor-phase epitaxy.

We have conducted a theoretical study of the equilibrium strain and misfit dislocation density profiles for “S-graded” buffer layers of InxGa1−xAs on GaAs (001) substrates in which the compositional profile follows a normal cumulative distribution function. On the basis of this modeling work we show that the S-graded layer exhibits misfit dislocation-free regions near the substrate interface and the free surface (or device interface). The equilibrium peak misfit dislocation density as well as the thicknesses of the dislocation-free regions may be tailored by design of the compositional profile; this in turn should enable minimization of the density of electronically active threading dislocations at the top surface. S-graded buffer layers may therefore facilitate the achievement of metamorphic device structures with improved performance compared with similar structures having uniform or linearly graded buffers.