Search

We experimentally demonstrated V-groove-based self-aligned SiN edge coupler (EC) on a monolithic CMOS-SiPh platform. 520 mW power handling capability were achieved.

We report the hybrid flip-chip integration of III-V laser on a monolithic silicon photonics (SiPh) platform. Wafer-scale laser attach was demonstrated with the assistance of a laser cavity on a Si substrate. The attach process was accomplished through precise optical and mechanical alignment features on the laser and SiPh wafer. Efficient laser-to-photonic integrated circuit (PIC) butt-coupling with optical power up to 11 dBm was achieved through a combination of precise mechanical stops and optical alignment features. Key laser performance metrics such as mode hopping and relative intensity noise (RIN) vs. reflectivity were also studied. The impact of laser-PIC alignment on the coupling efficiency was studied through comprehensive two-dimensional (2D) and three-dimensional (3D) numerical modeling. Simulations were also performed to explore different coupler designs for optimized laser coupling performance.

We report a hybrid flip-chip-integrated laser attach technology on a monolithic SiPh platform. Efficient laser-to-PIC butt-coupling with optical power up to 11dBm was demonstrated through a combination of precise mechanical stops and optical alignment features.

A beam shaping approach has been implemented to realize high-performance waveguide crossings based on cosine tapers. Devices with a compact footprint of 4.7 µm × 4.7 µm are implemented on a GLOBALFOUNDRIES monolithic silicon photonics platform. Fabricated devices are found to be nearly wavelength-independent (± 0.035 dB for 1260 nm ≤ λ ≤ 1360 nm) with low insertion loss (~ 0.2 dB) and crosstalk (< -35 dB). The measured response of the devices is consistent with simulation results obtained by 3D FDTD computations. The design stability is confirmed by measuring the device insertion loss over nine chips, which is found to be 0.197 ± 0.017 dB at the designed center wavelength of 1310 nm.

We review recent progress in loss reduction of Si and SiN waveguides in GLOBALFOUNDRIES 300mm monolithic Si photonics platform. Primary challenges to creating low-loss CMOS integrated photonic components are highlighted and potential solutions are outlined.

High-voltage ICs (HVICs) are used in many applications, including ac/dc conversion, off-line LED lighting, and gate drivers for power modules. This paper describes the technologies most commonly used in commercial HVICs, including junction-isolation, thin silicon-on-insulator (SOI), and thick SOI approaches. Emerging technologies such as thin silicon membrane are also discussed.

A beam shaping approach has been implemented to realize high-performance waveguide crossings based on cosine tapers. Devices with a compact footprint of 4.7 µ m × 4.7 µ m were fabricated on the GLOBALFOUNDRIES 45 nm monolithic silicon photonics platform (45 CLO technology). Fabricated devices are found to be nearly wavelength independent ( ± 0.035 d B for 1260 n m ≤ λ ≤ 1360 n m ) with low insertion loss ( ∼ 0.2 d B ) and crosstalk ( − 35 d B ). The measured response of the devices is consistent with the three-dimensional finite-difference time-domain simulation results. The design stability is validated by measuring the device insertion loss on eight chips, which is found to be 0.197 ± 0.017 d B at the designed center wavelength of 1310 nm.

Intelligent connected sensor and actuator endpoint nodes enable the Internet-of-Things (IoT). A brief overview of endpoint node functional blocks and requirements for low-power consumption are discussed. VLSI technology enablers for IoT include Ultra low Power (ULP) and Ultra Low Leakage (ULL) semiconductor process platform extensions. ULP and ULL implementations for bulk silicon technologies are presented and compared to fully-depleted silicon-on-insulator (FDSOI) technology. FDSOI utilizes Back Bias (BB) to improve performance and achieve the lowest dynamic and static power, enabling cost-effective low-power IoT applications.

For many decades the semiconductor industry has enjoyed the benefits of scaling. Every 2 years or so a new process node would arrive, bringing with it reduced area, along with improved performance and power. In recent years, we have seen and overcome many challenges to the scaling model, necessitating considerable efforts in VLSI circuits and technology. While we have largely maintained area scaling, obtaining even modest node-to-node improvements in performance and power has been difficult. New applications require much higher level compute than ever before which we are aiming to do via accelerators, programmable fabrics etc. These implementations respond very well with technology scaling. However, we are now approaching the biggest challenge yet. What happens when scaling slows to the point that it has, for practical purposes, stopped? How will we survive the post-scaling era? Our panel of experts, spanning VLSI technology, circuits, and business, looks at the difficulties ahead and potential ways forward.

In this paper a fully isolated bulk Si RF LDMOS device platform is reported which has been optimized for highly efficient mobile power conversion and RF power amplification. The self-aligned RF LDMOS NFET achieves a specific on-resistance R ds, on of 0.94 ohm-mm2, a breakdown voltage >9V, an R sp ∗Q gg product of 8.3 mohm nC, and a cutoff frequency F t > 43 GHz. Complementary PFET RF LDMOS exhibit an R ds, on of 3.6 ohm-mm2 with a cutoff frequency F t > 16GHz. Integrated DC-DC SMPS fabricated with these RF LDMOS have a 2.3x area reduction over conventional 5V CMOS and a gate driver efficiency increase of at least 75%. RF LDMOS NFET power amplifier cores (RF PA) under CW load pull and 3.3V supply voltage exhibit gains (Gt) of 18dB and 12dB at 2.4GHz and 5.8GHz, respectively, with a 1dB compression power density of 22dBm/mm of gate width and a maximum PAE > 70%. RF LDMOS power cells meet the 802.11n spectral mask requirement for a 20MHz 64 QAM modulated signal with P out = 19dBm. These DC and RF results are the best reported for integrated Si LDMOS device structures, enabling the next generation of highly efficient miniaturized mobile power converters and new RF integration paradigms for mobile front-end modules.

In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power management applications. The RF LDMOS NFET has demonstrated a drain-source turn-on resistance (R ds,on ) of 1.45ohm-mm, a cutoff frequency (Ft) greater than 40GHz and a drain-source breakdown down voltage (BV) in excess of 9V. For PA designs, the isolation layer is floating to reduce the parasitic and achieve high PAE/nonlinearity performance. RF power amplifier cores were fabricated and measured at 2.4GHz and 5.8GHz to demonstrate the RF LDMOS performance in PAs. Under CW loadpull and 3.3V supply, 18dB and 12dB gains (Gt) are achieved at 2.4GHz and 5.8GHz respectively, with 1dB compression point power density at 22dBm/mm gate width, and PAE > 63%, maximum PAE > 70%. Due to good model to hardware Pout correlation in a 5.8GHz PA cell, a fully matched PA last stage with the load-pull fundamental and harmonic impedances showed a less than 4° AM-PM phase distortion, meeting the 802.11n spectral mask requirement with 20MHz 64QAM modulated signal at 19dBm Pout.

A System-On-Chip (SOC) demonstrator integrating a low-noise IEEE 802.15.4 Transmitter and a DC-DC converter on a 0.18um High Voltage (HV) and RF CMOS process is presented in this paper. Noise isolation performance is critical to success of this type of SOC. A complete direct conversion transmitter was designed and various Quadrature VCO topologies were analyzed and compared based on the phase noise performance, device reliability, design robustness and image rejection. The final QVCO used in the transmitter has a FOM of 187dB, leading to an overall phase noise of −123dBc/Hz at 1MHz offset. The deep Nwell from HVCMOS process can be effectively used to provide isolation between the circuit blocks with measured results showing a sufficient noise isolation between the sensitive RF circuit and the switching 10MHz DC-DC converter.

A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3–7V.

While the semiconductor industry has contributed enormously to overall economic growth in the last 50 years, the coming decades will see IC innovation with much greater focus on so-called greener and leaner applications. We will witness an evolution from low power for long battery life to low overall power consumption. We will see more technology development away from the path of Moore?s Law geared to better control and management of our energy resources and improved power generation and storage. Energy used per kilometer of travel will continue to reduce as new semiconductor technology brings greater efficiency to conventional transport, and enables radically new vehicle architectures. The author overviews improvements in the areas of electronic equipment, automotive electronics, building controls, lighting, and photovoltaic systems that will contribute to a greener future. It is argued that the semiconductor industry (as other industries) can and will play its part in the drive to reduce global CO2 emissions, and help reduce climate change.

Microwave monolithic integrated circuit (MMMIC) technology using recrystallized silicon-on-insulator substrates would permit PIN diode phase shifters to be fabricated with higher power-handling capability and lower insertion loss than conventional MMIC control circuits using GaAs MESFETs. Moreover, at frequencies below 10 GHz, where substrate area requirements can be extensive, the silicon-on-insulator substrate technology can be less expensive. The research program stresses recrystallization of silicon-on-alumina films, followed by growth of silicon epitaxial layers and fabrication of surface-oriented PIN diodes. In the second year of the program, we have accomplished the following: (1) Recrystallization of silicon-on-alumina with various encapsulation and stress-relief layers, using both an electron-beam system and a graphite strip heater; (2) Evaluation of the effect of stress on film quality, which indicates directions for improved device-quality films; (3) Design and initial fabrication of surface-oriented PIN diodes on single crystal silicon to demonstrate device design concept; (4) Evaluation of future directions for the research program. This report covers the second-year results. Particularly noteworthy is the first recrystallization of silicon-on-alumina films and the first fabrication of surface-oriented PIN diodes with doped polysilicon handles for P+ and N+ injecting contacts.

We report a fiber-attach solution interfacing self-aligned, standard-cleaved fibers to monolithic photonic integrated circuits, fabricated in Globalfoundries 300-mm CMOS production facilities. Statistical yield analysis and reliability assessment were performed to demonstrate the robustness of the proposed solution.

A comprehensive set of SiN building blocks was demonstrated on a monolithic SiPh platform. Low-loss SiN waveguides (