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The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing network switching is to limit the consumption of dynamic power. Since dynamic power is one of the components of the total power consumed by digital systems, this leads to an optimization focused on the energy efficiency of digital systems. The basis of the proposed method is the technology mapping using a modified output graph describing the result of minimizing the multi-output function. The modified output graph, in terms of parameters associated with dynamic power, is defined as a switching graph. It was assumed that the key parameter associated with dynamic power is the switching activity of individual nodes of the logic network. The article presents elements of switching graph optimization which lead to the improvement of parameters associated with the dynamic power of the circuit. The essence of the proposed optimization methods is the appropriate movement of products and connections occurring in the logic network. Reducing the number of logic network vertices is also extremely important. The effectiveness of the proposed method was confirmed by the results of experiments performed on selected benchmarks. A significant reduction in the total value of switching activity was obtained for the optimized structures. [ABSTRACT FROM AUTHOR]

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits. [ABSTRACT FROM AUTHOR]

Technology mapping is an essential process in the Electronic Design Automation (EDA) flow which aims to find an optimal implementation of a logic network from a technology library. In application-specific integrated circuit (ASIC) designs, the non-linear delay behaviors of cells in the library essentially guide the search direction of technology mappers. Existing methods for cell delay estimation, however, rely on approximate simplifications that significantly compromise accuracy, thereby limiting the achievement of better Quality-of-Result (QoR). To address this challenge, we propose formulating cell delay estimation as a regression learning task by incorporating multiple perspective features, such as the structure of logic networks and non-linear cell delays, to guide the mapper search. We design a learning model that incorporates a customized attention mechanism to be aware of the pin delay and jointly learns the hierarchy between the logic network and library through a Neural Tensor Network, with the help of proposed parameterizable strategies to generate learning labels. Experimental results show that (i) our proposed method noticeably improves area by 9.3% and delay by 1.5%, and (ii) improves area by 12.0% for delay-oriented mapping, compared with the well-known mapper. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed research method is strictly aimed at further practical applications. The authors present the design technique aimed at the effective implementation of the modeled concurrent control system within the FPGA device. The main goal is the reduction in the logic resources of the destination FPGA by adequate modeling and optimization of the system. The proposed idea is illustrated by a real-life application of the photovoltaic control system implemented in the FPGA device from Xilinx (Artix-7 family). A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent control system is optimized by the use of the authors' techniques. The complete design flow is shown, including the modeling of the system by an interpreted Petri net, its further transformation to the hardware description language, adequate logic optimization, and final implementation within the destination FPGA. The presented method is explained by a case study example of the photovoltaic control system and compared with the already known technique. The performed experiments indicated a very high effectiveness of the proposed technique. It is shown that the photovoltaic control system designed according to the presented method reduces the logic resources of the destination FPGA device by up to 28%. [ABSTRACT FROM AUTHOR]

Abstract Phycocyanin (PC) is commercially exploited in various commercial sectors, as novel applications are developed rapidly. However, the state-of-the-art is difficult to define, given the extremely heterogeneous information available. Hence, this study aimed to perform a technological and scientific review on PC production from Spirulina (Arthrospira spp.), based on a bibliometric analysis of patents and research articles deposited from 2015 to 2023. To close the knowledge gap evidenced by the prospection, we optimized the instrumental conditions of microalgae cultivation, i.e., orbital agitation, culture volume, and cultivation time, for the production of PC. We assessed the color parameters and stability of the PC used as an ice cream colorant. The prospection highlighted rather diverse points of view between academia and the industry regarding PC production methods. The optimization showed a substantial impact of cultivation time on PC yield and purity. A purification step via precipitation was note necessary to obtain food-grade PC (purity > 0.7). Optimal experimental conditions were 180 rpm, 250 mL, and 14 days of cultivation. The ice cream colored using PC from the optimized cultivation conditions showed concentration-dependent color variations, without significant color losses for 90 days.

An extremely important aspect of the synthesis of digital circuits is obtaining solutions optimized in terms of energy consumption. This can be achieved by limiting the dynamic power, depending on the switching activity of the nodes of the implemented logic network. The article proposes a new technology mapping method leading to a reduction in switching activity. An approach known from the literature using an output graph was improved, the essence of which lies in the analysis of the created model of the switching system. The essence of this improvement was to take into account additional parameters related to switching the gateway network. The main contribution of the article is the use of a switching model in the form of an innovative switching graph to limit the number of switches of the logic network. The presented approach is focused on the sum-of-products (SOP) architecture. The reason for this choice is that it is the most elementary and universal form of mapping a combinational function, often implemented in some families of programmable devices. The proposed approach resulted in a significant reduction in switching activity compared to the classical implementation, by 68.9%, 70.6% and 70.2%, respectively, for SOP architectures with 3, 5 and 7 input sums. Of the 20 test systems considered, no significant improvement in switching activity was achieved compared to the classical method, only for 2, 3 and 4 cases, respectively, for SOP architectures with 3, 5 and 7 input sums. The results presented in the article confirm the effectiveness of the proposed methods.

In this study, we identify and forecast promising railway static inverter technologies and the technology taxonomy using patent data analytics. To this end, we identify technology topics through LDA topic modeling and interpret them through N-gram analysis. We then derive detailed promising technology topics through time series analysis and technology mapping. Finally, we identify leading companies and research institutes in the field of promising technology topics through bibliography and social network analysis of patent applicants. Our study identified six technology topics, and fields related to converter technology were identified as detailed promising technologies. Japanese companies represented by Mitsubishi, Hitachi, and Toshiba are leading R&D in this field, while Chinese companies represented by CRRC have also secured technological competitiveness. Additionally, France’s Alstom is technically competitive when considering only the centrality index. Our study will contribute to its use as a meaningful reference for the establishment of railway R&D and the development of promising railway static inverter technologies.

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits.

A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent control system is optimized by the use of the authors’ techniques. The complete design flow is shown, including the modeling of the system by an interpreted Petri net, its further transformation to the hardware description language, adequate logic optimization, and final implementation within the destination FPGA. The presented method is explained by a case study example of the photovoltaic control system and compared with the already known technique. The performed experiments indicated a very high effectiveness of the proposed technique. It is shown that the photovoltaic control system designed according to the presented method reduces the logic resources of the destination FPGA device by up to 28%.

This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented circuits represent the mapping of multi-output functions. Properly selected multi-output functions are described using a new form of the binary decision diagram (BDD), which is an extension of pseudomulti-terminal BDDs (PMTBDDs) in the literature. The essence of limiting power consumption is to include additional parameters during decomposition, such as the switching activity associated with the switching PMTBDD (SWPMTBDD). In addition, we highlight the key importance of circuit optimization methods via non-disjoint decomposition when minimizing power consumption. An algorithm is proposed to assess the effectiveness of decomposition, considering several parameters, such as the number of non-disjoint decompositions as well as that of shared and non-shared bound functions or the switching activity. The results of experiments that demonstrate the effectiveness of the proposed methods are also included.

Carbon dioxide capture, utilization, and storage (CCUS) technology is an emerging technology with large-scale emission reduction potential and an essential component of the global response to climate change to achieve net-zero goals. As the two most important countries in global climate governance, it is necessary to review and examine the current status and trends of research in the field of CCUS in China and the USA. This paper uses bibliometric tools to review and analyze peer-reviewed articles in the Web of Science from both countries during 2000–2022. The results show a significant increase in research interest among scholars from both countries. The number of publications in the CCUS field in China and the USA was 1196 and 1302, respectively, showing an increasing trend. China and the USA have become the most influential countries in CCUS. And the USA has a more significant academic influence on a global scale. Furthermore, the research hotspots in the field of CCUS are diverse and differentiated. That is, China and the USA pay attention to different research hotspots or have different focuses in different periods. This paper also finds that new capture materials and technology development, geological storage monitoring and early warning, CO2 utilization and new energy development, sustainable business models, incentive policies and measures, and public awareness are critical directions for future research in the field of CCUS, to provide a comprehensive review and comparison of CCUS technology development in China and the USA. It helps to gain insight into the research differences and linkages between the two countries in the field of CCUS and identify the research gaps between them. And place some consensus that policymakers can use. [ABSTRACT FROM AUTHOR]

The article discusses a synthesis strategy aimed at reducing power consumption consumed by logic structures implemented in FPGAs. The essence of the method is to carry out multioutput function decomposition, which takes into account the problem of dynamic power reduction. The article presents several techniques leading to such a reduction: preliminary ordering of variables taking into account the probabilities of occurrence of the value 1 for individual variables, reduction of the number of LUTs by limiting the number of bound functions, and in particular bicoding or appropriate unicoding taking into account the need to reduce power for the implementation of multioutput functions. These techniques have been combined into a coherent synthesis strategy called PowerdekBDD, which is an extension of the DekBDD strategy, which is the result of many years of work in the area of logic synthesis using BDD graphs. The article contains the results of experiments confirming the effectiveness of the presented strategy.

Researchers have long been interested in the transportation industry, recognizing its significant impact on human societies. Specifically, the automobile industry and its components have garnered special attention due to the evolving nature of transportation technologies. With this in mind, this study aims to explore the current and future technologies within the tire industry as a technological-based component of the automotive industry. Additionally, the research examines the key topics, leaders of technology, and strategies of technology-owning companies in these topics. To carry out this investigation, we employed a combination of methods including patent analysis and topic modeling. The selection of leading technology companies was based not only on the number of patents but also on the impact and quality of their patents, which was carefully evaluated. By leveraging these methods and results, tire companies and other industries can gain a competitive edge in technology, acquire insights into the current and future market share of leading companies, and develop effective roadmaps for their own advancement. • Patent based technology analysis on tire industry. • Latent dirichlet allocation application for topic identification. • R&D strategies derived from the analysis. [ABSTRACT FROM AUTHOR]

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers─as caused by the additional burden of artificial genetic circuits─shifts a cell's priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state model of gene expression, capturing characteristics like energy dissipation─which we link to the entropy production rate─and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit's functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energetic costs of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo .

The flexibility of field-programmable gate arrays (FPGAs) is attributed to the reconfigurability of their basic logic elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUTs) of $n$ inputs, that are designed to implement Boolean functions of $n$ or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of the decreased performance. This article proposes a new FPGA architecture, called threshold logic FPGA (TLFPGA), which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) (Muroga, 1987). Although TLCs implement a relatively small subset of Boolean functions known as threshold functions (Muroga, 1987), they require far fewer registers and multiplexers than an LUT, and are also significantly faster. This article describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40 and 28 nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture. [ABSTRACT FROM AUTHOR]

In the article, the authors describe their approach to creating regional nanotechnology development roadmaps. Original visualization and roadmaps for selected nanotechnologies are showcased. The creation of roadmaps was preceded by technology mapping and the selection of priority technologies, for which technology characteristics sheets were developed. Human resources (skills), financial resources, and tangible assets were a basis for the creation of the roadmaps specifying the development of priority nanotechnologies in the studied region (Podlaskie, Poland). The development of the technologies described in the roadmaps is stimulated by the R&D domain, which constitutes one of the roadmap layers. Potential technology application areas form the background for the “market” layer of the roadmaps. Segments related to the general development of a particular technology in time are additional elements enriching the roadmaps. All layers were presented in three-time perspectives. The conducted analysis served as a basis for the integration of the selected priority nanotechnologies into four nanotechnology development scenarios of the region. The obtained results contributed to the formulation of the Regional Nanotechnology Development Strategy. The research was conducted in a framework of the “Technological foresight ‘NT FOR Podlaskie 2020’ Regional strategy of nanotechnology development” project. [ABSTRACT FROM AUTHOR]

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems. [ABSTRACT FROM AUTHOR]

This paper presents an innovative method of technology mapping of the circuits in ALM appearing in FPGA devices by Intel. The essence of the idea is based on using triangle tables that are connected with different configurations of blocks. The innovation of the proposed method focuses on the possibility of choosing an appropriate configuration of an ALM block, which is connected with choosing an appropriate decomposition path. The effectiveness of the proposed technique of technology mapping is proved by experiments conducted on combinational and sequential circuits.

A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function. The main contribution is the novel multilevel optimization of an FSM. In this process, a new form of graph is used, i.e., a graph of excitations and outputs. This is a generalization of the graph of outputs that has previously been used in the process of technology mapping of multi-output functions in PAL-based programmable structures. The main idea, the theoretical background, and a precise algorithm are illustrated by means of simple examples. The proposed algorithm was compared with other approaches by synthesizing the FSM benchmarks and mapping the solutions to k-term PAL-based logic blocks. The obtained results are compared on the basis of the area (number of logic blocks) and speed (number of logic levels). The proposed approach is especially effective for larger FSMs.

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10-19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2 68x and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit. [ABSTRACT FROM AUTHOR]

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block. [ABSTRACT FROM AUTHOR]

In-memory computing has gained significant attention due to the potential for dramatic improvement in speed and energy. Redox-based resistive RAMs (ReRAMs), capable of non-volatile storage and logic operations simultaneously have been used for logic-in-memory computing approaches. To this effect, we propose ReRAM based VLIW Architecture for in-Memory comPuting (ReVAMP), supported by a detailed device-accurate simulation setup with peripheral circuitry. We present theoretical bounds on the minimum area required for in-memory computation of arbitrary Boolean functions specified using structural representation (And-Inverter Graph and Majority-Inverter Graph) and two-level representation (Exclusive-Sum-of-Product). To support the ReVAMP architecture, we present two technology mapping flows that fully exploit the bit-level parallelism offered by the execution of logic using ReRAM crossbar array. The area-constrained mapping (ArC) generates feasible mapping for a variety of crossbar dimensions while the delay-constrained mapping (DeC) focuses primarily on minimizing the latency of mapping. We evaluate the proposed mappings against two state-of-the-art technology in-memory computing architectures, PLiM and MAGIC along with their automation flows (SIMPLE and COMPACT). ArC and DeC outperform state-of-the-art PLiM architecture by $1.46\times$ 1. 46 × and $4.3\times$ 4. 3 × on average in latency. ArC offers significantly lower area (on average $25.27\times$ 25. 27 × and $6.57\times$ 6. 57 × ), while improving the area-delay product by $1.37\times$ 1. 37 × and $1.12\times$ 1. 12 × against two mapping approaches for MAGIC respectively. In contrast, DeC achieves average area ($1.45\times$ 1. 45 × and $3.06\times$ 3. 06 × ) and area-delay product ($1.12\times$ 1. 12 × and $6.36\times$ 6. 36 × ) improvements over the mapping approaches for MAGIC architecture respectively. The proposed mapping techniques allow a variety of runtime efficiency trade-offs. [ABSTRACT FROM AUTHOR]

In standard single flux quantum (SFQ) logic circuits, it is required to insert path balancing D-flip-flops (DFFs) to guarantee correct circuit operation. DFF insertion should be done in a way that any path from a primary input to a primary output has the same length in terms of the clocked element count. This is known as full path balancing (FPB) method. The FPB method usually requires insertion of many path balancing DFFs that can be even more than the actual gate count in the original circuit. This significantly increases the chip area, lowers the local clock frequency, and increases both static and dynamic power dissipation. This article presents an architecture for realizing SFQ circuits which removes all path balancing DFFs, resulting in a huge reduction in total area, node and Josephson junction count, and power consumption. The drawback is a degradation of the peak throughput of the circuit, which can be overcome by performing partial path balancing in the circuit, thereby recovering the circuit throughput by adding some path balancing DFFs. [ABSTRACT FROM AUTHOR]

Decomposition is a technology-independent process, in which a large complex function is broken into smaller, less complex functions. The costs of two-level or factored-form representations (cubes and literals) are used in most decomposition methods, as they have a high correlation with the area of cell-based designs. However, this correlation is weaker for field-programmable gate arrays (FPGAs) based on look-up tables. Furthermore, local optimizations have limited power due to the structural bias of the circuit descriptions. This paper tries to reduce the structural biasing by remapping the look-up table network and decomposing the derived functions using the support as cost function. The proposed method improves the FPGA mapping results of a commercial tool for the 20 largest MCNC benchmarks, with gains of 28% in delay plus 18% in area when targeting delay, and a reduction of 28% in area plus 14% in delay with area as cost function. Results with 23% less area and 6% less delay are obtained after physical synthesis (post place-and-route). Moreover, 12 of the best known results for delay (and 3 for area) of the EPFL benchmarks are improved. [ABSTRACT FROM AUTHOR]

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases.

This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this paper are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filters and restructure these units to achieve improved integration levels. The technology optimized Boolean networks are then coded using instantiation based coding strategies. The Xilinx tool then uses its own optimization strategies to further optimize the networks and generate circuits with high logic densities and reduced depths. Experimental results indicate a significant improvement in performance over traditional realizations. An important property of technology-dependent optimizations is the simultaneous improvement in all the performance parameters. This is in contrast to the technology-independent optimizations where there is always an application driven trade-off between different performance parameters.