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A promising candidate for 3-D solid-state storage is a vertical racetrack memory (VRM) which is capable of storing hundreds of bits within a tiny footprint. The stored bits are able to shift spintronically along the racetrack. However, their probabilistic movement inflicts positional errors, manifested as random bit deletions (or insertions) that necessitate Varshamov-Tenengolts (VT) codes which are able to correct these positional errors. VT syndrome generation (SG) is an iterative process and its latency grows linearly with the length of a VRM cell. In this article, we focus on the parallelization of SG, in order to bring a dramatic reduction in latency. We propose a radix-2 SG that processes a pair of data bits simultaneously in its compute engine, effectively reducing the number of iterations to half. The incident data block is partitioned and the two bits are selected from different partitions which are either stacked or folded. This partition space is explored with mathematical and architectural viewpoints in this work. The careful evaluation shows that a radix-2 folded SG is superior to other choices as it not only achieves the anticipated 50% reduction in delay, but also dramatically reduces the energy consumption when compared with recent state-of-the-art syndrome generators.

This paper considers the problem of anomaly detection in an outdoor environment where surveillance cameras are usually installed to monitor activities of general public. A novel solution is proposed which combines audio and visual data to automatically detect abnormal activities. The proposed anomaly detection algorithm makes use of both visual and audio features to automatically detect anomalous activities in scenes. Visual features such as optical flow technique combined with particle swam optimization and social force model are used, whereas, acoustic features such as, energy, zero crossing rate, volume, spectral-centroid, spectral spread, spectral roll-off, spectral flux, cross correlation and the mel-frequency cepstral coefficients (MFCCs) are used. An anomaly inference is developed which is based on both visual and audio features. The performance of the proposed algorithm is evaluated by testing it on the publicly available UMN datasets combined with the audio recordings. The proposed algorithm is compared with state-of-the-art techniques and is shown to achieve improved performance in terms of accuracy.

Global navigation satellite systems have been used for reliable location-based services in outdoor environments. However, satellite-based systems are not suitable for indoor positioning due to low signal power inside buildings and low accuracy of 5 m. Future smart homes demand low-cost, high-accuracy and low-power indoor positioning systems that can provide accuracy of less than 5 m and enable battery operation for mobility and long-term use. We propose and implement an intelligent, highly accurate and low-power indoor positioning system for smart homes leveraging Gaussian Process Regression (GPR) model using information-theoretic gain based on reduction in differential entropy. The system is based on Time Difference of Arrival (TDOA) and uses ultra-low-power radio transceivers working at 434 MHz. The system has been deployed and tested using indoor measurements for two-dimensional (2D) positioning. In addition, the proposed system provides dual functionality with the same wireless links used for receiving telemetry data, with configurable data rates of up to 600 Kbauds. The implemented system integrates the time difference pulses obtained from the differential circuitry to determine the radio frequency (RF) transmitter node positions. The implemented system provides a high positioning accuracy of 0.68 m and 1.08 m for outdoor and indoor localization, respectively, when using GPR machine learning models, and provides telemetry data reception of 250 Kbauds. The system enables low-power battery operation with consumption of &lt, 200 mW power with ultra-low-power CC1101 radio transceivers and additional circuits with a differential amplifier. The proposed system provides low-cost, low-power and high-accuracy indoor localization and is an essential element of public well-being in future smart homes.

The advancements in Edge computing have paved the way for deep learning in real-time systems. One of the beneficiaries is an adaptive traffic control system that responds to real-time traffic observations by governing the signal phase and timings. Reinforcement Learning (RL) is extensively utilized in the literature in order to decrease traffic congestion in a road network. However, most of the previous works leverage centralized and cloud-based RL due to the computational complexity of underlying deep neural networks (DNN). Therefore, a persistent challenge towards adopting Edge learning is in devising a Multi-Agent RL in which agents are simplified, and their state spaces are localized but they perform comparable to the centralized RL. This article presents a Collaborative and Adaptive Signaling on the Edge (CASE), a novel Multi-Agent RL approach to control the traffic signals’ phase and timing. Each signalized intersection in the road network is provided with an Edge Learning Platform which hosts an RL-Agent that observes local traffic states and learns an optimum signal policy. Moreover, CASE allows collaboration among RL-Agents by sharing their signal phase and timings to achieve convergence and performance. This collaboration is limited to one’s direct neighbours only to minimize the computational complexity. We performed rigorous evaluations in terms of the choice of RL methods and their state space/reward and found that our collaborative state-space has resulted in a performance comparable to a centralized RL yet with a cost similar to the decentralized RL. Finally, a performance comparison of the CASE controller ported to the state-of-the-art Edge learning platforms is presented in this article. The results show that the proposed CASE controller can achieve real-time performance when ported to a general-purpose GPU-based platform. This arrangement achieves more than 8 times improvement in computational time over conventional embedded platforms.

Polycrystalline samples with formula Bi1−xBaxFeO3 (x = 0.0–0.25) were fabricate by solid state reaction technique. Synchrotron XRD diffraction confirmed that the rhombohedral structure is transformed to pseudo cubic. The Mossbauer spectra inferred the existence of only Fe3+ ions, these results also indicated the destruction of spiral spin structure with increasing Ba doping level. The magnetic measurements showed that the coercive field is increased from 22.4 to 2600.2 Oe and the remnant magnetization is increased from 0.67 μemu/g to 0.49 emu/g on increasing Ba concentration. This increase in ferromagnetism can be attributed to the destruction of spiral spin structure, which is indicated from the Synchrotron XRD and Mossbauer results.

Spintronic racetrack memory stores binary information in magnetic domains, isolated with domain walls and movable within a nanowire. Because the domain wall motion is probabilistic, Varshamov–Tenengolts (VT) codes have been applied to such devices due to their ability to correct single-bit deletion and insertion. The complexity of the VT encoder and decoder is largely because of a sequential syndrome calculator that employs modulo-additions. Previous implementations avoided this complexity by restricting the racetrack size to a specific number of magnetic domains. In this letter, we describe an efficient implementation of the syndrome calculator with a novel steering algorithm, which not only alleviates the above-mentioned restrictions but also reduces adder size and the required number of operations, exploiting modulo-arithmetic symmetries in VT codes. We synthesize the syndrome calculator with varying number of domains to show that the algorithm is scalable, increases areal efficiency, slashes processing time, and lowers the power consumption of a VT encoder and decoder.

Recent interest in CMOS voltage scaling has produced a class of cache architectures which tolerate parametric SRAM failures at low voltage by substituting faulty words of one cache line with healthy words of another line. These caches rely on the fault maps (which grow reciprocally with smaller word sizes) for fault identification. Therefore, the benefits of cache voltage scaling must be rigorously investigated against the cost of their fault map overheads, especially in large caches. This paper reviews the word substitution caches and develops their parametric failure model. Our developed model leads to a non-intrusive and reconfigurable cache (Macho) which can be locally optimized (based on local fault density) by two graph-based algorithms. Specifically, our adaptive matching algorithm increases effective cache capacity by dynamically concentrating healthy cache blocks into active cache sets. Macho enables voltage scaling down to 400mV by tolerating high SRAM-failure rates (≥ 1%) and achieves better energy reduction (44%) than other substitution caches with similar area overheads.

Continuous scaling in CMOS fabrication process makes circuits more vulnerable to process variations, which results in variable delay, malfunctioning, and/or leaky circuits. Caches are one of the biggest victims of process variations due to their large sizes and minimal cell features. To mitigate the impacts of process variations on caches, we propose to localize the effects of process variations at a word level, not at the conventional cache set, cache way, or cache line level. Faulty words are disabled or shut down completely and accesses to those words are bypassed to a small set of word-length buffers. This technique is shown to be effective in reducing performance penalty due to process variations and in increasing the parametric yield up to 90% when subjected to the performance constraints.

Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a number of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages. These schemes rely on the fault maps to identify faulty words, inevitably increasing the chip area. Besides, the relationship between word sizes and the cache failure rates is not well studied in these works. In this paper, we analyze the word substitution schemes by employing Fault Tree Model and Collision Graph Model. A novel cache architecture (Macho) is then proposed based on this model. Macho is dynamically reconfigurable and is locally optimized (tailored to local fault density) using two algorithms: 1) a graph coloring algorithm for moderate fault densities and 2) a bipartite matching algorithm to support high fault densities. An adaptive matching algorithm enables on-demand reconfiguration of Macho to concentrate available resources on cache working sets. As a result, voltage scaling down to 400 mV is possible, tolerating bit failure rates reaching 1 percent (one failure in every 100 cells). This near-threshold voltage (NTV) operation achieves 44 percent energy reduction in our simulated system (CPU $+$ DRAM models) with a 1 MB L2 cache.