This article presents a multi-standard transmitter based on the eight-path architecture with a fully digital baseband (BB) input, covering the frequency band from 300 MHz to 1.5 GHz, while all harmonics and the distortion product of C-IMD3 are rejected to better than −40 dBc. The proposed architecture is based on the multipath technique in which the amplitude weighting algorithm is implemented in the digital domain. The fully digital input baseband section of the architecture eliminates the need for power-consuming circuit modules, such as mixers, high-frequency filters, and amplifiers, thus simplifying the required circuitry and improving the overall performance in terms of the operating frequency band, power consumption, and power efficiency. The power amplifier of this transmitter consists of an array of four pseudo-differential digital power amplifiers. A programmable first-order radio frequency (RF)-low pass filter (LPF), integrated within the DPAs, as well as an off-chip first-order RF-LPF, has been adopted in order to attenuate the seventh and ninth harmonics below the desired level, which are not rejected by the eight-path architecture. The chip is realized in 0.18- $\mu \text{m}$ CMOS with an active area of 0.58 mm 2. Measurements verify an output power and overall power efficiency ranging from 10.6 to 17.6 dBm and 3.6% to 19.7%, respectively, within the entire RF bandwidth. The proposed transmitter also satisfies the requirements of the IEEE 802.11af and IEEE 802.11ah standards. An ANN-based calibration algorithm improves the error vector magnitude of 64-QAM data from −21.5 to −34.1 dB.