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This work demonstrates the advantage of carrying out silicon ion (Si+) implantation at high temperatures for forming controlled heavily doped regions in gallium oxide. Room temperature (RT, 25 °C) and high temperature (HT, 600 °C) Si implants were carried out into MBE grown (010) β-Ga2O3 films to form ∼350 nm deep Si-doped layers with average concentrations up to ∼1.2 × 1020 cm−3. For such high concentrations, the RT sample was too resistive for measurement, but the HT samples had 82.1% Si dopant activation efficiency with a high sheet electron concentration of 3.3 × 1015 cm−2 and an excellent mobility of 92.8 cm2/V·s at room temperature. X-ray diffraction measurements indicate that HT implantation prevents the formation of other Ga2O3 phases and results in reduced structural defects and lattice damage. These results are highly encouraging for achieving ultra-low resistance heavily doped Ga2O3 layers using ion implantation.

We present recent work on design, fabrication, and characterization of thin-film, flexible superconducting stripline cables. Fabrication details, dc, and microwave performance (up to 14 GHz) of cables with Al/Nb/Al conductors and polyimide (PI) dielectric are discussed. Thin Al was used as a barrier layer between Nb and polyimide to protect the Nb superconductivity during subsequent PI curing steps, which were performed at a reduced temperature. The dc performance, including critical transition temperature and critical current, of the stripline transmission lines is presented. We observed T c values of ~8.8 and ~8.6 K for signal traces and ground planes, respectively. Microwave characterization, including cross-talk, was performed on stripline transmission lines and resonators. We observed reasonable impedance match (S 11 better than -15 dB), low insertion loss (S 21 better than 0.04 dB/cm) and cross-talk below -60 dB for stripline transmission lines measured up to 10 GHz at 4.2 K. Furthermore, similarly fabricated stripline resonators exhibited quality factors ~7 000 at 10 GHz and 1.2 K for stripline resonators. The results of these experiments provide insight into material stack-ups for robust, multi-layer superconducting flexible cables that can find use in future cryogenic electronics systems.

Flexible interconnects with superconducting (SC) traces and polyimide dielectric can provide low signal loss and low thermal conductivity at cryogenic temperatures, and are expected to find use in densely integrated cryogenic electronics systems. The ultra-low loss of SC interconnects at microwave frequencies can be accurately characterized through the use of weakly coupled SC resonators. The high-quality factor resonators provide sensitive measurements of the aggregate loss properties of the conductor and dielectric, as functions of frequency, temperature, and signal power. In this work, resonators with different linewidths were fabricated and tested to study how the linewidth impacts the overall internal resonator loss, in order to better characterize and separate the individual loss components (i.e., dielectric loss vs. conductor loss). The results of this work are important for understanding loss and transmission properties of similarly designed and fabricated transmission line interconnects.

The titanomagnetites (Fe

We have investigated the displacement damage (DD) effect on the electrical characteristics of ZnO thin film transistors (TFTs) based on its location of origin in the device structure. The area subjected to the maximum proton dose induces a maximum DD effect in that particular location. ZnO TFTs with two different passivation layer thicknesses were prepared to obtain maximum proton dose distribution in either the ZnO channel layer or ZnO/SiO2 interface. The devices were irradiated by a proton beam with an energy 200 keV and 1 × 1014 protons/cm2 fluence. Transport of Ions in Matter (TRIM) simulation, followed by calculation of depth distribution of the nonionizing energy loss (NIEL), illustrated different proton dose distribution profiles and NIEL profiles along the depth of the device for these two types of samples. The sample with the maximum proton dose peaks at the ZnO/SiO2 interface exhibited a significant degradation in device electrical characteristics as compared to the negligible degradation of the sample when the maximum proton dose was absorbed in the ZnO layer. Therefore, the investigation into the radiation hardness of proton-irradiated ZnO TFTs is non-trivial since the displacement damage induces drastic changes on the device characteristics based on the damage location.

In this work, we investigate the effect of borosilicate glass (BSG) as gate dielectric on dielectric/4H-SiC interface traps and channel mobility in 4H-SiC MOSFETs. The interface trap characterization by C−ψs analysis and I-V characterization show lower fast interface trap density (Dit) as well as significant improvement of channel field-effect mobility on devices with BSG than that on devices with standard NO anneal. In addition, the results indicate interface trap density decreases with increasing B concentration at the interface of BSG/4H-SiC, which in turn, results in higher channel mobility.

In this letter, it is demonstrated that 4H-SiC MOSFETs with borosilicate glass (BSG) as the gate dielectric result in significantly higher channel mobility than standard nitride oxide annealed devices, due to lower density of near-interfacial traps at the BSG/SiC interface. Using a thin Antimony-doped surface layer in conjunction with the BSG dielectric results in higher channel mobility at room temperature. The field-effect channel mobility of such devices is found to be 180 ${\rm {cm}}^{{2}}/{\text {V}}\cdot \text {s}$ at low transverse electric fields (close to threshold) and 94 ${\text {cm}}^{\text {2}}/{\text {V}}\cdot \text {s}$ at high fields (~2 MV/cm), which is about a factor of five higher than the state-of-the-art. This, along with a tunable threshold voltage, could make this approach very attractive for power MOSFET applications. However, the poor bias temperature instability of BSG is a big challenge for utilization of this dielectric.

The titanomagnetites (Fe2-xTixO4,x⩽ 1) are a family of reducible spinel-structure oxides of interest for their favorable magnetic, catalytic, and electrical transport properties. To understand the stability of the system during low temperature deposition, epitaxial thin films of Fe2TiO4were deposited by molecular beam epitaxy (MBE) on MgO(001) at 250-375 °C. The homogeneous incorporation of Ti, Fe valence state, and film morphology were all found to be strongly dependent on the oxidation conditions at the low substrate temperatures employed. More oxidizing conditions led to phase separation into epitaxial, faceted Fe3O4and rutile TiO2. Less oxidizing conditions resulted in polycrystalline films that exhibited Ti segregation to the film surface, as well as mixed Fe valence (Fe3+, Fe2+, Fe0). A narrow window of intermediate oxygen partial pressure during deposition yielded nearly homogeneous Ti incorporation and a large fraction of Fe2+. However, these films were poorly crystallized, and no occupation of tetrahedral sites in the spinel lattice by Fe2+was detected by x-ray magnetic circular dichroism at the Fe L-edge. After vacuum annealing, a small fraction of Fe2+was found to occupy tetrahedral sites. Comparison of these results with previous work suggests that the low temperature deposition conditions imposed by use of MgO substrates limits the incorporation of Ti into the spinel lattice. This work suggests a path towards obtaining stoichiometric, well-crystallized Fe2TiO4by MBE by utilizing high substrate temperature and low oxygen partial pressure during deposition on thermally stable substrates.

Biocompatible solid electrolyte chitosan is introduced as a protonic/electronic electric double layer (EDL) dielectric in a multilayer MoS2 transistor. This chitosan-bioinspired transistor can operate at a low working voltage (

The use of phosphorous as a passivating agent for the SiO2/4H-SiC interface increases the field effect channel mobility of 4H-SiC MOSFET to twice the value, 30-40cm2/V-s, that is obtained with a high temperature anneal in nitric oxide (NO). A solid SiP2O7planar diffusion source is used to produce P2O5for the passivation of the interface. Incorporation of phosphorous into SiO2leads to formation of phosphosilicate glass (PSG) which is known to be a polar material causes device instability. With a new modified thin phosphorous (P) passivation process, as described in this abstract, we can improve the stability of MOSFETs significantly with mobility around 75cm2/V.s.

4H-Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) are enabling high-efficiency power switching applications under high-temperature, and harsh environment conditions because of SiC’s superior physical properties. However, 4H-SiC MOSFETs have a much lower channel conductance due to the trapping of electrons by a high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface [1,2]. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Among the many approaches to solve this issue, using atomic layer deposition (ALD) of high k-dielectrics such as Al2O3 is promising. It has been reported that appropriate surface termination of 4H-SiC prior to ALD with hydrogen [3,4] or SiO [5,6] results in improved properties of Al2O3/4H-SiC MOS devices. The SiO termination refers to the insertion of an ultra-thin (~0.7 nm) silicon oxide layer between Al2O3 and 4H-SiC that results in effective channel mobility greater than 250 cm2Vs-1[5, 6]; significantly higher than that obtained by using standard nitrided (NO annealed) [7] SiO2 as the gate dielectric. In this work, we studied the above two surface termination approaches for ALD Al2O3 using electrical characterization and compared to typical thermally grown SiO2. To this end, Si-face n-type 4H-SiC MOS capacitors were fabricated and characterized using the simultaneous high-low frequency capacitance-voltage (CV), current-voltage (IV) and constant capacitance deep level transient spectroscopy (CCDLTS). For H- termination, prior to ALD, samples were etched in H2 at 1600 ◦C followed by annealing in H2 at 1000 ◦C [3, 4]. Following this, ALD was performed at 200 °C using Trimethylaluminum (TMA, Al(CH3)3) as the precursor to deposit ~50 nm of Al2O3. Electrical measurements were carried out after patterning and deposition of Au/Ti gates. In these samples, the interface state density (Dit ~3x1011 cm-2eV-1) near the conduction band edge was comparable to nitrided SiO2 as shown in Fig. 1. In addition, the CCDLTS showed that the typical ‘O1’ and ‘O2’ NITs[8] detected by CCDLTS at 4H-SiC/SiO2 interfaces, with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV[4,8] below the 4H-SiC conduction band, were absent at these Al2O3/4H-SiC interfaces (Fig.2), which is extremely encouraging. In the second surface termination approach, ultra-thin (2O3 deposition. Different oxidation conditions were employed varying the furnace temperature as 550 ◦C, 600 ◦C and 650 ◦C with 5 min oxidation time. Then, ~40 nm Al2O3 was deposited using the above ALD process and Al gate contacts were formed. Figure 3 shows the typical quasistatic CVs. It can be clearly observed that, with increasing oxidation temperature, the CV curves shift to the left indicating a reduction of negative charges at the interface, consistent with Dit reduction. However as shown in Fig.1, the simultaneous high-low CV reveals much higher Dit for these devices (~1x1013 cm-2eV-1 near the conduction band edge), comparable to typical unpassivated thermal oxides. Previous reports suggest that the ultra-thin oxide film thickness should be about ~0.7 nm to obtain low Dit and high channel mobility [5,6]. Our preliminary XPS analysis suggests that our film thickness is less than this critical value which might be the cause of the higher Dit here. Therefore, within our current results, we observe that surface H-termination prior to ALD of Al2O3 results in significantly lower Dit compared to SiO termination. Further studies with thicker SiO interlayers will be presented at the conference along with chemical bonding results from XPS analysis. Acknowledgments: This work was supported by the II-VI Foundation and US Army Research Lab. The authors thank Drs. Chunkun Jiao and Koushik Ramadoss from Purdue and Drs. Leonard C. Feldman and Ryan Thorpe from Rutgers University for sample fabrication and XPS analysis. [1] T. Kimoto, and J. A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley, 2014. [2] B. J. Baliga, Fundamentals of power semiconductor devices,1st edn., Springer, US, 2010. [3] T. Seyller, Appl. Phys. A. 85. 4. 371–385, Dec. 2006. [4] I. Jayawardhena, A. Jayawardena, C. Jiao, D. Morisette, and S. Dhar, Materials Science Forum, Proceedings of the 2018 ECSCRM (accepted 2019) [5] T. Hatayama, S. Hino, N. Miura, T. Oomori, and E. Tokumitsu, IEEE Trans. Electron Devices. 55. 8. 2041–2045. 2008. [6] J. Urresti, F. Arith, S. Olsen, N. Wright, and A. O’Neill, IEEE Trans. Electron Devices,66, 4, 1710–1716, Apr. 2019. [7] G. Y. Chung et al., Appl. Phys. Lett. 76. 13. 1713–1715, 2000. [8] A. F. Basile, J. Rozen, J. R. Williams, L. C. Feldman, and P. M. Mooney, J. Appl. Phys., 109, 6, 064514, Mar. 2011. Figure 1

We describe a superconducting (SC) cable-to-cable connection method for thin-film flexible (Nb/polyimide) parallel transmission line cables that exhibits low loss from DC to microwave frequencies. Design, fabrication procedures, assembly methods and characterization results are reported. The connector assembly incorporates a monolithic array of short superconductive bridging traces that function as a ganged electrical splice between two ribbon cables. The assembly is micro-mechanically self-aligned and uses pressure to make simultaneous electrical contacts between multiple 50 μm wide microstrip signal traces, as well as between ground planes. Each contacting surface comprises thin SC Nb overcoated with ultra-thin Au, providing nearly zero DC resistance and very good RF performance. A simulation model of the microwave performance of microstrip-to-microstrip interconnections at 4.2 K was successfully matched to measurement results. This new cable-to-cable connection approach exhibited an insertion loss 15 dB up to 14 GHz. The connections performed reproducibly throughout multiple thermal cycles and multiple disassembly/reassembly cycles.

An electroless nickel film contains 5-14% by weight of phosphorus. Because of the presence of such a high concentration of phosphorus, electroless nickel can be a useful and convenient source of phosphorus dopant in the fabrication of n-type ohmic contacts for SiC. This paper describes the successful deposition of a Ni:P layer on 4H-SiC through electroless nickel plating followed by a discussion of the results of surface science and electrical measurements. Specific contact resistivity on lightly-doped samples with carrier concentration of 2.5 ´ 1016 cm-3 has been found to be about 4.8 ´ 10-6 Ωcm2 without any need for ion implantation. This metallization technique is especially useful in broad area ohmic contact formation on the back of n-type SiC substrate.

Proton irradiation-induced effects on AlGaN/GaN high electron mobility transistors (HEMTs) were studied by emulating a certain space radiation environment (upstream of the earth's bow shock) using a relatively low energy (100 keV) proton beam with fluences of 1 × 1010, 1 × 1012, and 1 × 1014 protons/cm2. In order to isolate radiation-induced effects produced by the modification of the epi-layer from the effects produced by the change in the device structure (such as contacts), the epi-layers were irradiated prior to device fabrication, followed by material/device characterization. Proton irradiation-induced sub-gap traps were detected by spectroscopic photo current-voltage measurement. Raman study revealed that the proton irradiation had induced strain relaxation on the AlGaN/GaN HEMTs epi-layer. No substantial change in the crystal quality of the epi-layer was indicated by Raman and PL studies. With increasing proton fluences, increasing charge carrier density was observed, which was estimated via Raman spectroscopy and the charge-control model analysis. The magnitude and direction of the transistor threshold voltage shift were also dependent on proton fluence. Overall, degradation of transistor output characteristics of the fabricated HEMTs was observed with increasing proton fluence. However, based on the observed performance and the level of influence on material/device characteristics by 100 keV protons, it can be suggested that the AlGaN/GaN HEMTs have high endurance for exposure to relatively high fluences of the low-energy proton beam.

Films of CuInSe2 (CIS) and CuGaSe2 (CGS) were deposited on (100) Si by radiofrequency (RF) magnetron sputtering from stoichiometric CIS and CGS targets. Rutherford backscattering (RBS) analysis yielded a composition of Cu0.8In1.1Se1.9 for CuInSe2, which indicates that these films were Cu and Se poor. A composition of Cu0.3Ga1.5Se2.0 for CuGaSe2 shows Ga-rich and Cu-poor layers. Transmission electron microscopy (TEM) of cross-sectional samples established that the films were polycrystalline in nature and free of pinhole defects that normally short-circuit devices fabricated on glass with submicron absorber layers. From the electron and x-ray diffraction patterns, tetragonal chalcopyrite phases of the material were identified. Circular diodes, with a diameter between 100 μm and 400 μm, were fabricated on the grown films with a common Au back-contact. Diodes on both CIS and CGS films exhibited rectifying characteristics. From the polarity corresponding to the high and low currents, it was inferred that the grown films were p-type. These diodes exhibited photovoltaic response, and the forward-bias current increased by as much as two orders of magnitude when illuminated by a 75-W halogen lamp. The open-circuit voltages (VOC) for these devices are expected to approach the turn-on voltage of the diodes, 0.5 V and 0.7 V, for the CGS/Si and the CIS/Si heterojunctions, respectively. Shunting caused by degenerate phases present in the CGS film is believed to have resulted in the observed lower turn-on voltage for the CGS/n-Si heterojunction diode.

The field of SiC electronics has progressed rapidly in recent years, but certain electronic properties remain poorly understood. For example, a consensus has not been reached as to the specific point defects which limit minority carrier recombination, and little is known about defects which limit generation lifetimes. This paper investigates generation lifetimes using the pulsed MOS capacitor technique and compares the results with defect densities, recombination lifetimes, and Schottky diode characteristics in the same material for the first time. Carrier generation lifetimes in 4H-SiC epilayers range from less than 1 ns to approximately 1 μs and depend strongly on measurement conditions and data interpretation. They are limited by dislocations only at densities higher than 106 cm-2.The only point defect that is theoretically capable of limiting generation lifetime to the levels currently observed in 4H-SiC is EH 6/7. However, this defect cannot account for the case where generation lifetimes are lower than recombination lifetimes in the same area. This is not seen in silicon and seems to be inconsistent with theory. Possible reasons for these perplexing results are discussed, and it is attempted to form a framework with which further understanding of the significance of carrier generation lifetime measurements in SiC can be achieved.

4H-Silicon carbide is one of the enabling materials for modern high voltage and high temperature power electronic devices due to its attractive material properties. A significant drawback to SiC MOSFET performance is the low channel conductance due to trapping of carriers by the high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Constant capacitance deep level transient spectroscopy (CCDLTS) technique is appropriate for analysis of such defects as it can differentiate between trap types and measure trapped charge emission rates. In this study, we examined SiO2-4HSiC interfaces formed on the polar (0001) Si- face (100% Si) and non-polar (11-20) a-face (50% Si, 50% C) oriented 4H-SiC wafers using CCDLTS. For the NO annealed Si-face interface, there are two main types of NITs detected by CCDLTS, labeled “O1” and “O2” traps by Basile et al. [1]. The physical identities of these defects have been suggested to be carbon dimers substituted for O dimers (CO=CO) and interstitial Silicon atoms in the near interfacial SiO2[2]. In this work, we observed both the O1 and O2 traps in the Si-face with activation energies of about 0.15±0.01 eV and 0.35±0.01 eV respectively, which are consistent with previous results[3]. The original result obtained in this study was that for the a-face; two new NITs (labeled A1 & A2) positioned very close to the O1 peak were observed but the O2 peak was absent. For this study, 4H-SiC MOS capacitors were fabricated on Si-face and a-face oriented wafers. The samples underwent dry oxidation followed by nitridation with NO annealing at 1175°C. After that, circular Al gates were evaporated as gate contact. The oxide thickness was ~62 nm and ~54 nm for Si-face and a-face respectively. CCDLTS was measured on capacitors keeping a constant capacitance in deep depletion in a temperature range of 77 K to 298 K changing pulse voltages and emission rates. Using the analysis method detailed in [1], the activation energies of the A1 and A2 peaks were found to be 0.15±0.01 eV and 0.19±0.01 eV respectively, which is in the same range as the O1 trap in the Si-face. The capture cross-sections for all traps detected was in the 10-16-10-14 cm2 range. Qualitatively, this result is similar to the results reported in [4], which shows that nitrided SiO2 formed on the (000-1) C-face (100% C terminated) also shows only one peak very similar to the O1 trap observed on the Si-face. This result points to the importance of interface structural differences due to different wafer orientation with respect to near-interface oxide traps. Acknowledgement: This work was supported by the II-VI foundation References: [1] A. F. Basile, J. Rozen, J. R. Williams, L. C. Feldman, and P. M. Mooney, J. Appl. Phys., 109, 064514, 2011. [2] P. Deák, J. M. Knaup, T. Hornos, C. Thill, A. Gali, and T. Frauenheim,” J. Phys. Appl. Phys., 40, 6242, 2007. [3] P. M. Mooney, Z. Jiang, A. F. Basile, Y. Zheng, and S. Dhar, J. Appl. Phys., 120, 034503, 2016. [4] T. Hatakeyama, M. Sometani, Y. Yonezawa, K. Fukuda, H. Okumura, and T. Kimoto, Jpn. J. Appl. Phys., 54, 111301, 2015.

Samples for transmission line model (TLM) and Hall measurements were fabricated on (0001) 4H-SiC implanted with nitrogen at 1 × 1018 cm−3, 4 × 1018 cm−3, 1 × 1019 cm−3, 4 × 1019 cm−3, and 1 × 1020 cm−3. Following high-temperature activation, the activation percentage dropped from ~90% to ~20%, and the Hall mobility decreased from ~100 cm2/V · s to ~20 cm2/V · s as the implant concentration increased from 1 × 1018 cm−3 to 1 × 1020 cm−3. The specific contact resistance as a function of Hall concentration is compared with published data for Ni contacts to epitaxial layers. The specific contact resistance as a function of activation temperature was also studied for two fixed implant concentrations of 5 × 1018 cm−3 and 1 × 1020 cm−3.

Metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated on the carbon face of 4H-SiC were characterized following different postoxidation annealing methods used to passivate the oxide–semiconductor (O–S) interface. Of the various processes studied, sequential postoxidation annealing in NO followed by atomic hydrogen gave the lowest interface trap density (D it). Direct oxidation/passivation in NO yielded somewhat better I–V characteristics, though all passivation ambients produced approximately the same breakdown field strength. n-Channel MOSFETs showed high channel mobility at low field, which is likely caused by the presence of mobile ions at the O–S interface. Comparisons with the silicon face are presented for interface trap density, oxide breakdown field, and channel mobility. These comparisons suggest that the carbon face does not offer significant performance advantages.

High-temperature processing was used to improve the barrier properties of three sets of n-type 4H-SiC Schottky diodes fabricated with Ni Schottky contacts. We obtained an optimum average barrier height of 1.78 eV and an ideality factor of 1.09 using current–voltage measurements on diodes annealed in vacuum at 500°C for 24 h. Nonannealed contacts had an average barrier height of 1.48 eV and an ideality factor of 1.85. The Rutherford backscattering spectra of the Ni/SiC contacts revealed the formation of a nickel silicide at the interface, accompanied by a substantial reduction in oxygen following annealing.

The pulsed MOS-C (Metal Oxide Semiconductor-Capacitor) technique was used to measure generation lifetimes in 4H-SiC epitaxial wafers. The ratio of generation to recombination lifetime has been investigated to understand the dominant defect for generation lifetime. The EH6/7 defect level is considered to limit generation lifetime and field enhanced emission is proposed to explain extremely large variation of generation lifetime in a small area. Generation lifetime is limited by dislocations when they are above a threshold density of about 106cm-2. Generation lifetimes measured on 4 and 8 degree off-cut angle epi-substrates are very comparable.

The operation of metal-oxide-semiconductor (MOS) devices based on the semiconductor SiC in high temperature environments above 300 °C requires an understanding of the physical processes in these capacitor structures under operating conditions. In this study we have focused on the regime of inversion biasing, where the electrical characteristics of the device are dominated by minority carriers. We report on the direct observation of the high frequency inversion capacitance due to thermal generation of holes in 6H-SiC n-MOS capacitors between 450 and 600 °C by monitoring the 1MHz C-V characteristics of large area, 1000 μm diameter, capacitors in the dark. Our experimental results are consistent with a first order calculation based on the delta depletion approximation.

Compared to silicon, there have been relatively few comparative studies of recombination and carrier lifetimes in SiC. For the first time, both generation and recombination carrier lifetimes are reported from the same areas in 20 m thick 4H SiC n-/n+ epi-wafer structures. The ratio of the generation to recombination lifetime is much different in SiC compared to Si. Activation energy calculated from SiC generation lifetimes shows that traps with energy levels near mid-gap dominate the generation lifetime. Comparison of both generation and recombination lifetimes and dislocation counts measured in the device area show no correlation in either case.

Thermal oxides on the Ga-face of low defect density bulk gallium nitride (GaN) were controllably produced under varying conditions and subsequently analyzed. The thermal oxidation was performed in a dry oxygen atmosphere at different temperatures and different oxidation times. Each oxide layer was identified as the monoclinic β-Ga2O3 by a θ–2θ X-ray diffraction (XRD) scan. Complementary Auger electron spectroscopy (AES) and high-resolution X-ray photoelectron spectroscopy (XPS) were also performed to study the chemical and electronic states of the oxide. The surfaces of the as-grown oxide and the GaN surfaces (after oxide removal) were studied using scanning electron microscopy (SEM). The roughness of both surfaces was found to increase with increasing oxidation temperature. Schottky diodes were fabricated on the GaN surfaces after oxide removal to further examine the surface quality. An excess reverse leakage current was found for Schottky diodes fabricated on GaN surfaces that were oxidized at 950 °C or 1000 °C, indicating possible surface decomposition at these two temperatures. The characteristics of wet and dry etching of the gallium oxide layer were also investigated. Finally, metal–oxide–semiconductor (MOS) capacitors were fabricated using thermally oxidized bulk GaN substrates. Current–voltage (I–V) measurements showed a low reverse current of 1.5 pA at −10 V. The oxide breakdown field was determined to be 0.65 MV/cm. Capacitance–voltage (C–V) measurements displayed a deep depletion feature, and the interface trap density near the conduction band was estimated to be in the low 1011 eV−1 cm−2 range.

A new method for precisely measuring low gate oxide currents by measuring the charge leaking through the oxide in a pulsed metal oxide semiconductor capacitor (MOS-C) is presented. Using basic equipment, it is possible to measure currents less than 10 fA/cm2 . The relevant theory is developed to use these capacitance-time data to extract an approximate leakage current and the effect on the extracted generation lifetime. The technique is simple and requires the same equipment used for pulsed MOS-C generation lifetime measurements. Experimental results are presented, which are consistent with theory.

The radiation tolerance of strained Si/SiGe n-MODFETs is investigated, using 10 keV X-rays, 63 MeV high energy protons, and 4 MeV low energy protons. The effects of radiation exposure on two major device design parameters (LSD and LG) in T-gate Si/SiGe n-MODFETs devices are examined. A strong dependence on source-drain spacing is observed for both the DC and RF characteristics. A drift-diffusion TCAD framework is used for 2-D device simulations. We believe that the low energy protons damage the SiGe/strained-Si/SiGe lattice, leading to partial strain relaxation. The conduction band-offset (CBO) of the strained SiGe/Si heterojunction is lowered leading to higher gate current leakage. The presence of radiation-induced bulk traps in the unrelaxed SiGe layers on the device behavior is also investigated.

We report on improved electrical properties and thermal stability of ZrB2 Schottky contacts deposited on n-type 4H-SiC at temperatures between 20°C and 800°C. The Schottky barrier heights (SBHs) determined by current-voltage measurements increased with deposition temperature, from 0.87 eV for contacts deposited at 20°C to 1.07 eV for those deposited at 600°C. The Rutherford backscattering spectroscopy (RBS) spectra of these contacts revealed a decrease in oxygen peak with an increase in the deposition temperature and showed no reaction at the ZrB2/SiC interface. These results indicate improved electrical and thermal properties of ZrB2/SiC Schottky contacts, making them attractive for high-temperature applications.

In this work, we have investigated the effect of Antimony counter-doping in channel region of 4H-SiC MOSFETs with moderately doped p-body, relevant for power applications. Using this process, improved sub-threshold slope and high channel mobility have been achieved in conjunction with high threshold voltage. Our results indicate that the improvement in transport is associated with Sb donors close to the surface, which have negligible effect on interface trap density.

Post-oxidation anneals that introduce nitrogen at the SiO2/4H-SiC interface have been most effective in reducing the large interface trap density near the 4H-SiC conduction band-edge for (0001) Si face 4H-SiC. Herein, we report the effect of nitridation on interfaces created on the (11 20) a-face and the (0001) C-face of 4H-SiC. Significant reductions in trap density (from >1013 cm-2 eV-1 to ~ 1012 cm-2 eV-1 at EC-E ~0.1 eV) were observed for these different interfaces, indicating the presence of substantial nitrogen susceptible defects for all crystal faces. Annealing nitridated interfaces in hydrogen results in a further reduction of trap density (from ~1012 cm-2 eV-1 to ~5 x 1011 cm-2 eV-1 at EC-E ~0.1 eV). Using sequential anneals in NO and H2, maximum field effect mobilities of ~55 cm-2 V-1s-1 and ~100 cm-2 V-1s-1 have been obtained for lateral MOSFETs fabricated on the (0001) and (11 20) faces, respectively. These electronic measurements have been correlated to the interface chemical composition.

Silicon has been the semiconductor of choice for microelectronics largely because of the unique properties of its native oxide (SiO2) and the Si/SiO2 interface. For high-temperature and/or high-power applications, however, one needs a semiconductor with a wider energy gap and higher thermal conductivity. Silicon carbide has the right properties and the same native oxide as Si. However, in the late 1990’s it was found that the SiC/SiO2 interface had high interface trap densities, resulting in poor electron mobilities. Annealing in hydrogen, which is key to the quality of Si/SiO2 interfaces, proved ineffective. This paper presents a synthesis of theoretical and experimental work by the authors in the last six years and parallel work in the literature. High-quality SiC/SiO2 interfaces were achieved by annealing in NO gas and monatomic H. The key elements that lead to highquality Si/SiO2 interfaces and low-quality SiC/SiO2 interfaces are identified and the role of N and H treatments is described. More specifically, optimal Si and SiC surfaces for oxidation are identified and the atomic-scale processes of oxidation and resulting interface defects are described. In the case of SiC, we conclude that excess carbon at the SiC/SiO2 interface leads to a bonded Si-C-O interlayer with a mix of fourfold- and threefold-coordinated C and Si atoms. The threefold coordinated atoms are responsible for the high interface trap density and can be eliminated either by H-passivation or replacement by N. Residual Si-Si bonds, which are partially passivated by H and N remain the main limitation. Perspectives for the future for both Si- and SiC-based MOSFETs are discussed.

SiC based field-effect devices are attractive for electronic and sensing applications above 250 °C. At these temperatures the reliability of the insulating dielectric in metal-oxidesemiconductor (MOS) structures becomes an important parameter in terms of long-term device performance. We report on the reliability of n-MOS SiC capacitors following thermal stress cycling in the 330 to 630 °C range. As the primary mode of oxide breakdown under these conditions is believed to be due to electron injection from the substrate, the gate leakage current was measured as a function of temperature. The gate dielectric was grown using dry oxidation with a post oxidation NO passivation anneal. For large area, 1 mm diameter, 6H-SiC capacitors we obtain current densities as low as 5nA/cm2 at 630 °C. In addition, gate leakage measurements from arrays of 300 to 1000 2m diameter devices fabricated on different 1cm2 6H-SiC substrates are presented. These are encouraging results for the long-term reliability of SiC field-effect sensors.

We have studied the effect of ion-beam irradiation on reducing the ordering temperature of FePt and FePtAu nanoparticles. FePt and FePt(Au14%) 4 nm particles dispersed on a Si-substrate were irradiated by 300 keV Al-ions with a dose of 1 × 1016 ions/cm2 at 43 °C using a water-cooled flange in order to minimize the vacancy migration and voids formation within the collision cascades. Partial chemical ordering has been observed in as-irradiated particles with coercivity of 60–130 Oe. Post-irradiation annealing at 220 °C enhanced chemical ordering in FePt nanoparticles with coercivity of 3500 Oe, magnetic anisotropy of 1.5 × 107 erg/cc, and thermal stability factor of 130. A much higher 375 °C post-irradiation annealing was required in FePtAu, presumably because Au atoms were trapped at Fe/Pt lattice sites at lower temperatures. As the annealing temperature increased, anomalous features in the magnetization reversal curves were observed that disappeared at higher annealing temperatures.

Low interface trap density and high channel mobility on nonpolar faces of 4H-SiC, such as the (11[2]0) a-face, are of fundamental importance in the understanding of SiC MOS devices. It is also critical for high-voltage trench power MOSFET development. We report new results on the passivation of the SiO2/a-face 4H-SiC interface using phosphorus, yielding field effect mobility of ~125 cm2/V · s. We also revisit the conventional NO passivation, for which a mobility of ~85 cm2/V · s was achieved on the a-face. These results not only establish new levels of mobility in SiC MOSFETS but also lead to further insights into factors currently limiting SiC inversion layer mobility.

Phosphorous from P2O5 is more effective than nitrogen for passivating the 4H-SiC/SiO2 interface. The peak value of the field-effect mobility for 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) after phosphorus passivation is approximately 80 cm2/V·s. However, P2O5 converts the SiO2 layer to phosphosilicate glass (PSG)-a polar material that introduces voltage instabilities which negate the benefits of lower interface trap density and higher mobility. We report a significant improvement in voltage stability with mobilities as high as 72 cm2/V·s for MOSFETs fabricated with a thin PSG gate layer ( ~ 10 nm) capped with a deposited oxide.

The radiation response of SiO 2 gate oxides grown on 4H-SiC to NO passivation is presented for the first time. The effects of gamma radiation on Q eff are similar for n-4H-SiC MOS capacitors both with and without NO passivation, but are different in sign (negative) compared to SiO 2 on Si. The variation in D it with total dose, however, is different for the passivated versus the unpassivated samples. Comparisons between Si SOI and 4H-SiC suggest that properly passivated SiC MOSFETs should have good radiation tolerance.

We present the first investigation of low energy (1.75 MeV) proton irradiation in SiGe HBT's and discuss proton energy effects in SiGe HBT technology. The results show that after 1.75 MeV 1 /spl times/ 10/sup 14/ p/cm/sup 2/, a semi-insulating substrate is obtained and the peak quality factor of the monolithic inductors is improved by about 18% at 1.6 GHz. Although large current gain degradation for the SiGe HBT's was observed in the RF bias region after 1 /spl times/ 10/sup 14/ p/cm/sup 2/, the degradation in peak f/sub T/ is only about 11%. Proton energy studies from 1.75 MeV to 200 MeV in SiGe HBT's suggest that the conventional damage factor can be used to estimate energy-dependent proton-induced radiation damage in this technology.

We report the structural and magnetic properties of Ni films grown on GaAs(001) using electrodeposition, covering the thickness range 0–80 nm. The structure is characterized by mixed (001) and (011) epitaxial orientation of fcc Ni with a preference for the Ni(001) orientation. The magnetic anisotropy is originated by a combination of a crystalline contribution with fourfold symmetry and a uniaxial anisotropy probably caused by the asymmetry in the substrate surface structure. The saturation magnetic moment varies linearly with thickness, indicating limited intermixing between Ni film and GaAs substrate. This is ascribed to the low-energy deposition process characteristic of electrodeposition.

Alloys of aluminum and titanium have been successfully used to form low resistance ohmic contacts to p-type SiC. While the 90 wt.% Al alloy has been studied extensively, the literature does not reveal any work which indicates whether the 90/10 or any other alloy composition is the best alloy for use as an ohmic contact material to p-SiC. This work systematically looks at four different Al–Ti alloy compositions in an attempt to decide which alloy if any is superior as an ohmic contact material. The alloy compositions that were studied were chosen by examining the binary Al–Ti phase diagram and choosing specific phases prior to reaction with the SiC. It will be shown that only alloys which have some amount of a liquid phase present at the anneal temperature will form an ohmic contact to p-type SiC.

4H- Silicon carbide is a promising for power electronic devices operated at high voltages, high temperatures, and high frequencies due to its attractive material properties, such as high avalanche electric breakdown field (2.5 MV/cm), high electron mobility (1000 cm2/V. s), high thermal conductivity (4.9 Wcm-1K-1) and large bandgap (3.26 eV). While conventional double-implanted MOSFET (D-MOSFET) has been commercially successful, trench MOSFET is a fascinating device design for next-generation 4H-SiC power MOSFETs due to its low specific on resistance (RON) [1] and higher current density which can potentially reduce cost. Trench formation in mechanically hard and chemically stable 4H-SiC material requires reactive ion etching (RIE). This RIE step has been reported to introduce surface roughness and deep level defects [2-4] in SiC which may cause degradation of the channel mobility as well as the voltage blocking capability of the trench MOSFETs. These particular issues are critical challenges and need further attention. In this regard, we have studied the electrical properties of planer MOS capacitors fabricated on Si-face () and A- face () 4H-SiC epitaxial layers, with and without RIE, prior to gate oxidation. Capacitance coupled plasma (CCP) RIE process was carried out to etch about 2μm of SiC, using NF3as the process gas. Before performing the gate oxidation, a sacrificial thermal oxidation was carried out on the etched samples to consume subsurface damage. The gate oxidation was followed annealing in nitric oxide (NO) for both etched and un-etched samples. Atomic force microscope (AFM) images revealed that almost atomically flat surfaces (RMS roughness= 0.3 nm) were obtained following RIEs as shows in Figure 1. Simultaneous high-low capacitance-voltage (C-V) measurements at room temperature was carried out to investigate RIE induced effects on effective charge density at the SiO2/4H-SiC interface and the interface trap density (Dit ) near the conduction band-edge of 4H-SiC. In addition, current-voltage (I-V) measurements were done at room temperature to investigate RIE induced dielectric breakdown effects. From the room temperature C-V data as shown in the Figure 2, it can be seen that C-V curves for MOS capacitors with or without RIE lie on top each with negligible flat-band voltage (VFB ) shift which suggests that the effective interfacial charge does not change significantly due to RIE (Table 1). Furthermore, extracted Dit profiles (Figure 3) with or without RIE MOS capacitors also shows no difference. In addition, comparable I-V data as shown in the Figure 4 also confirmed minimal effects induced by RIE. These results are inconsistent with previous results [4] where RIE was shown to generate significant amount of interface traps. This is most likely due to a much smoother surface obtained here after RIE as well the post-RIE sacrificial oxidation step which was implemented here. These results suggest that processes such as etching in an H2 environment at elevated temperatures not be necessary after RIE for trench MOSFET fabrication. In the ongoing work, we are analyzing possible deep level defects in the SiC bulk, introduced by RIE using deep level transient spectroscopy measurements. In this talk, detailed discussion of the methods in the context of trench MOSFETs and analysis of the obtained results will present. [1] B. J. Baliga, Fundamentals of power semiconductor devices 2010 (Springer Science & Business Media) [2] V. Khemka et al.: J. Electron. Mater. 27 (1998) 1128-1135 [3] K. Kawahara et al.: J. Appl. Phys. 108 (2010) 023706 [4] Gang Liu et al.: Appl. Surf. Sci. 324 (2015) 30–34 Figure 1

In this work, we investigate the effect of Boro-silicate glass (BSG) gate dielectric in conjunction with Antimony (Sb) surface doped channels of lateral 4H-SiC MOSFETs. It has been reported that BSG gated 4H-SiC MOSFETs have a high channel mobility of ~100 cm2/V∙s for a wide range of surface transverse electric fields along with a large threshold voltage VT of ~5V in lightly doped p-epitaxial layers [1,2]. For vertical power MOSFETs with heavily doped p-wells, it is expected that BSG would cause an even further increase of VT (~10 V) which would be undesirable. Therefore in this work, our goal for combining the Sb surface doping process (demonstrated in our earlier works [3,4] and presented at ECSCRM 2014 [4]), with BSG gate dielectric was two-fold: (i) Tune VT to adequate value with high sub-threshold slope. (ii) Achieve high low-field channel mobility by Sb counter-doping while retaining the high-field mobility characteristics of BSG. The results from our experiments indicate that these goals were achieved. The 'Sb+BSG' process results in significant improvement of both low-field channel mobility to ~180cm2/V∙s (due to addition of Sb surface doping) and high-field channel mobility to ~90 cm2/V∙s (due to the BSG gate dielectric) along with a tuned threshold voltage of ~2V and a steeper sub-threshold slope. Lateral MOSFETs were fabricated on the Si-face of p-type 4H-SiC epitaxial layers doped at ~1x1016cm-3. Sb was implanted in the channel region with 80 keV at room temperature with dose of 2.5x1013cm-2, which results in a Gaussian profile with a depth of around 30nm below the surface of SiC. This was followed by post-implantation activation annealing at 1650°C using a graphitic carbon cap layer. Next, dry oxidation at 1150°C for 10 hours was performed followed by post-oxidation annealing using a planar diffusion source (Techneglas, GS-139) composed of boric oxide (B2O3) in a gas mixture of Ar (50sccm) and O2 (5sccm) at 950°C for 30 mins. Samples that received only boron annealing are referred to as 'BSG only' and samples underwent both Sb counter-doping and boron annealing are referred to as 'Sb+BSG'. Results for these samples are compared with standard NO-annealed devices in Table Ⅰ. The SIMS result in Fig. 1 shows B distributes throughout the oxide with a concentration of ~1x1022cm-3 and decreases as it reaches SiC. Threshold voltage and sub-threshold slope were characterized by Id-Vg measurement at room temperature and field-effect mobility was extracted from the transconductance of Id-Vg curve. Linear and log scale of Id-Vg curves in Fig. 2 and Fig. 3 demonstrate that 'Sb+BSG' tunes the threshold voltage to a more desirable value of ~2V along with a better sub-threshold slope than standard NO annealing. Fig. 4 shows a significant mobility improvement for 'Sb+BSG' at both high field due to the BSG passivation effect and low field due to the Sb counter-doping effect with a peak value of ~180cm2/V∙s compared to 'BSG only' with a peak mobility of ~140cm2/V∙s. In order to investigate the boron passivation effect on interface traps, C-V and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on the companion BSG capacitors. The interface trap density of 'NO' was determined to be ~2.5 times higher than that of 'BSG' for very shallow energy traps ( References [1] D. Okamoto, M. Sometani, S. Harada, R. Kosugi, Y. Yonezawa, and H. Yano, IEEE Electron Device Lett. 35, 12 (2014). [2] T. Isaacs-Smith, Y. Zheng, C. Jiao, A. C. Ahyi, and S. Dhar, 2016 MRS Spring Meeting & Exhibit, Phoenix, Arizona, 4 (2016). [3] A. Modic, G. Liu, A. C. Ahyi, Y. Zhou, P Xu, M. C. Hamilton, J.R Williams, L. C. Feldman, and S. Dhar, IEEE Electron Device Lett.35, 894 (2014). [4] A. C. Ahyi, A. Modic, C. Jiao, Y. Zheng, G. Liu, L. C. Feldman, and S. Dhar, Materials Science Forum, Vols. 821-823, (2015) pp. 693-696. [5] Xiao Shen, and Sokrates Pantelides, 11th annual SiC MOS workshop meeting, UMD College Park, August 15, 2016. Figure 1

As the laminate substrate industry moves from hot air solder level (HASL) finishes, alternate plating finishes are being proposed such as immersion gold/electroless nickel, electroless palladium, and electroless silver. This paper presents results of an evaluation of the thermosonic gold ball wire bondability of electroless palladium. Two palladium thicknesses, with and without a nickel underlayer, were evaluated from two vendors. In each case, a thin gold passivation layer was deposited by immersion plating over the palladium. The initial evaluation criteria included bondability (number of missed bonds and flame off errors), wire pull strength, standard deviation, bond failure mode, and visual inspection. The bonding window was determined by independently varying force (four levels), power (four levels), and time (two levels). The stage temperature was maintained at 150/spl deg/C, compatible with BT laminate material. Different preconditioning environments such as a solder reflow cycle, high temperature storage (125/spl deg/C) and humidity storage (85%RH/85/spl deg/C) on initial bondability were also considered. Rutherford backscattering and Auger analysis were used to examine the surface finishes. The stability of the bonds was investigated by high temperature storage (125/spl deg/C) with periodic electrical resistance and pull strength testing.

Results are reported for ohmic contacts formed on n-type 4H and 6H-SiC using nichrome (80/20 weight percent Ni/Cr). The electrical characteristics of these NiCr contacts are similar to those of contacts formed on 6H-SiC using pure Ni (∼1×10−5Ω-cm2 for moderately doped material), but the contacts exhibit significant improvement with regard to physical stability. Composite Au/NiCr contacts exhibit good stability during long-term anneals (∼2500 h) at 300°C without the requirement of a diffusion barrier layer between the NiCr ohmic contact layer and the Au cap layer. In addition, the use of NiCr results in success rates near 100% for direct wire bonding to the Au cap layers. Characterization of the contacts by Auger electron spectroscopy, Rutherford backscattering spectroscopy, and transmission electron microscopy provides an explanation for the observed behavior.