Search

Solar cell performance at low light intensity is practically important for power generation capacity in the entire life cycle. Our previous study demonstrated that glass frit, which is an indispensable constituent in paste for metallization of the cells, decreases the performance at low light intensity by causing shunts and recombination in the cells. Furthermore, our study has shown that aluminum in silver/aluminum paste for the metallization of n-type solar cells affects the reaction system among silver, glass frit, and silicon substrate during the firing process; as a result, aluminum mitigates shunts and recombination due to the paste. Thus, it can be possible that the aluminum mitigates the degradation of the low light performance due to the glass frit, because it has been reported that the performance of solar cells with low shunt resistance becomes lower at low light intensity. For this reason, in this study, the effects of aluminum on shunts, recombination, and low light performance of the cells due to glass frit are investigated. In conclusion, the aluminum decreases the recombination caused by the glass frit, resulting in mitigation of a decrease in open-circuit voltage and an increase in series-resistance due to the frit; then, the aluminum alleviates the degradation of the solar cell performance due to the frit at low light intensity.

Contacting silver paste for an emitter of silicon solar cells has been pointed out to create shunting and to increase carrier recombination due to silver-crystallites at the emitter. However, since these observed electrical losses come of not only the crystallites but also multiple effects of constituents in the paste, whether the crystallites mainly cause these losses has still remained unknown. In this study, how glass frit “itself,” which is most important constituent in the paste, affects the electrical losses is investigated by applying the “floating contact method.” Furthermore, the contact interface between the frit and silicon surface is also investigated to elucidate the mechanism of the losses. The metal oxide glass frit itself is found to drastically cause the shunting and the recombination in n-type solar cells, resulting in loss in open-circuit voltage, and creates metal lead crystallites through redox reaction at silicon surface during firing. The shunting originates from the metallic lead, and the recombination is induced by diffused impurities or defects into the silicon emitter through the reaction. The electrical losses in the solar cells are led to not only by the silver-crystallites, but also by the glass frit itself.

Reduction of the contact resistance at source/drain and metal electrodes is one of the key challenges in the fabrication of high performance CMOS devices. In recent years, several studies have addressed the issue of minimizing the specific contact resistivity (ρ c ) [1] – [5] . Quite low values of ρ c in the sub-10 −9 ohm-cm 2 region have been reported for advanced technologies.

In a long history of photovoltaic innovations, various architectures of crystalline silicon solar cells have been evolved to result in the highest conversion efficiency (η) of those days as described in Best Research Cell Efficiency by NREL. The cells are characterized by three parameters of the power max (Pmax), the saturation current (Jsc) and open-circuit voltage (Voc), but the fill-factor (FF) can be deduced from those three parameters. The 36 outstanding cells of those days are picked up from the published papers to be plotted on the η-FF and η-Jsc•Voc planes, in which all kinds of the architectures of the cells are included, for instance, PERC, PERL, PERT, HIT, IBC, TopCon, POLO, POLO-IBC, and Hetero-IBC(HJ-IBC). The plots of the η of those outstanding solar cells against their FF or Jsc•Voc clearly reveal a linear relation among them, even they have been independently evolved. The linear relation seems to have some effective meanings. The linear relation being assumable as a straight line, a 87% of FF on the line, which was predicted as the limit of FF by M. Reusch, can meet well with 29% to 30% in efficiency, which have been expected as the efficiency limit of crystalline silicon solar cells by W. Schockley and J. Queisser, and R. Swanson.

Solar cell performances at low light intensity are practically more important for power generation capacity in the entire life cycle. Previous studies have revealed that efficiency and maximum power of the solar cells with low shunt resistance become lower at the low light intensity. In contrast, our study has demonstrated the effects of paste or glass frit as paste constituents on shunts and recombination, as well as open-circuit voltage of solar cells with floating contact method. However, the effects of the glass frit in the paste on the low light performances of the cells have not been actually clear yet. For this reason, in this study, the effects of the glass frit itself on the low light performances of the cells are investigated. This is because even though the glass frit is an indispensable constituent for silver paste to electrically contact to the solar cells, the effects of the glass frit itself on cell performance have not been clear yet. In conclusion, the glass frit itself makes the solar cell performances lower at the low light intensity, especially open-circuit voltage and fill factor, by causing shunts and recombination, which means that the effects of paste constituents on shunts and recombination are important not only for solar cell performances at 1 sun, but also for the performances at low light intensity.

Silver/aluminum (Ag/Al) paste has been used as metallization for p + emitter of n-type solar cells. Nevertheless, the Ag/Al paste induces junction current leakage or shunting in the solar cells, resulting loss in open circuit voltage (V oc ). However, the details still are not known about how glass frit and aluminum in the paste affect the p + emitter, and result in the electrical losses, respectively. Furthermore, it is not still clear whether and how the aluminum addition induces the electrical losses. In this study, the “floating contact method” proposed by R. Hoenig was applied for the measurement to investigate the respective effect of glass frit and aluminum on the electrical losses. Conductive paste with the glass frit for the p + emitter induces loss in V oc of the cells even if the paste contains no aluminum. The glass frit in the Ag/Al paste induces carrier recombination and significant shunting of p-n junction, but the aluminum in the paste mitigates these electrical losses because of weakening emergence of Ag-crystallites on the p + emitter.

Vehicle horns must satisfy sound pressure level regulations in each country. Therefore, it is essential to optimize the horn location inside the front grille of the vehicle to maximize sound transmission through the grille opening and adhere to sound pressure level regulations. This study developed a computational method to determine optimal horn locations during early stages of vehicle development to reduce the number of trials during later stages. Therefore, an analytical model based on a one-dimensional standing-wave model was established using parameters obtained in the early stages. Subsequently, spectral changes were predicted for the transfer characteristics based on the horn location (i.e., from the horn to the exterior of the front grille). The analytical model was validated by comparing computed spectral images with those obtained experimentally from sample commercial vehicles. Image correlations between the analytical model and experimental results were greater than 80%. The high correlation suggests that the analytical model sufficiently represented the sound propagation phenomena, including transmission from the front grille. Finally, the model results established the optimal horn placement, which was validated using a commercial vehicle as a case study. The placement obtained by the proposed analytical model was in good agreement with that of the commercial vehicle.

A new direct detection technique for silanol is needed for tribological materials containing silicon. We focused on near-edge X-ray absorption fine structure (NEXAFS), which uses synchrotron radiation as a method for directly detecting silanol. Model samples were prepared, and their spectra were obtained by NEXAFS. The Si and the O K-edge spectra of silanol exhibited peaks at approximately 1843 eV and 535 eV, respectively. Then the surfaces of silicon-containing diamond-like carbon (DLC-Si) films were measured. The amount of silanol on high-silicon-doped DLC, which had a low friction coefficient, was found to be greater than that on low-silicon-doped DLC. In this research, we demonstrated that the silanol on the surface of DLC-Si films can be directly detected and identified by NEXAFS.

We used Flash Lamp Annealing (FLA) to control dopant diffusion in the nm range in n+/p germanium junctions. The diffusion of phosphorus was slower when co-doping with fluorine at doses below 2×1014 cm−2 compared to a sample without F doping. The diffusion lengths in samples with and without F were 6.7nm and 9.1nm, respectively. In addition, precise diffusion control below 7nm could be achieved without degrading the activation level in the sample with F doping. Owing to the slow rate of diffusion, this has quite a low impact on the deactivation of P. By co-doping F with boron, diffusion in the nm range can be achieved, demonstrating the potential for controlling B diffusion in Ge. Thus, ion implantation and FLA can be usefully applied in Ge CMOS fabrication processes.

We studied N+/P junction formation in germanium by various ion species systematically. We evaluated the effect of co-implantation of C, Al and Sn in detail. It should be emphasized that the trade-off relationship between Rs and Xj can be overcome by Sn co-implantation, although a slight increase in Rs value was observed. Diffusion of phosphorus can be controlled by Sn co-implantation technique. We also evaluated the residual defects and stress generation of Sn co-implantation.

Flash Lamp Annealing (FLA) is a well-known technique for millisecond annealing. In forming ultra-shallow junctions, FLA can provide high activation levels with precise diffusion control in the nanometer range. Currently, devices with 3D structures require conformal doping as well as diffusion control. Sol-Gel Coating (SGC / Tokyo Ohka Kogyo Co., Ltd.) has a special feature, in that a very thin film on the nanometer scale can be deposited on a 3D structure. In this work, we used SGC as a dopant source and FLA to demonstrate that highly activated junctions can be formed, and effective doping can be realized. Thus, this doping technique can be applied to advanced 3D devices, such as logic, memory and CMOS image sensor.

We are developing a new flash lamp annealing (FLA) system featuring flash lamps with short duration and high output power for all CMOS technology nodes including advanced devices. With this system, we can realize lower thermal budgets and higher peak temperatures (jump temperature). Our conventional FLA tool has a wide range of annealing conditions, with annealing times from 0.8 to 100 ms. The duration of the FLA conditions of the system we are developing can be extended to deep sub-millisecond levels, making it complementary to our conventional tool. In this report, we present initial data from a new prototype system. The data clearly demonstrate that higher activation can be achieved. Notably, supersaturated activation of 4.6×1020 cm−3 can be achieved with only slight diffusion of 5.8 nm in a p+/n Si junction. In addition, Hall effect measurements revealed higher carrier concentrations of up to 1020 cm−3 in polycrystalline Si (poly-Si). These results show that the new system has the potential for forming highly activated junctions with minimal diffusion in Si and poly-Si and can contribute to the fabrication of high performance devices.

Metallization contacts on emitter of silicon solar cells cause shunting of p-n junction and induce carrier recombination, resulting in a loss in open-circuit voltage Voc of the cells, which must severely limit cell efficiency. But, the mechanism of the shunting and the recombination has not been understood enough yet, especially on the contacts with conductive paste, because the shunting and the recombination caused by the paste come of multiple effects of each constituent in the paste such as silver metal, glass frit, and some additives. Thus, the effects of the each constituent in the paste should be clarified to elucidate the mechanism and to achieve an advanced paste for high-efficiency silicon solar cells. In our previous study, effects of aluminum in silver/aluminum paste and effects of glass frit itself on the shunting and the recombination in n-type solar cells were clearly shown by using “floating contact method”, and its effectiveness on the paste evaluation were demonstrated in the solar cells. In this study, the floating contact method was applied to conventional p-type solar cells with silver paste to clarify effects of tellurium oxide on the silver paste, because the detailed effects of the tellurium oxide on the shunting and the recombination have not been clear yet even though the oxide is widely used for commercial paste. Our study clearly shows that the tellurium oxide reduces the shunting and the recombination caused by the silver paste in the solar cells, and also demonstrates the effectiveness of the floating contact method on the paste evaluation.

Silicon semiconductor devices have remarkably been improved by the process scaling and introduction of some boosting technologies such as high-k/metal gate and strained silicon. However further improvement is quite difficult from the view point of mobility of silicon material. To overcome this problem, an increasing amount of attention has been devoted to the investigation of some higher carrier mobility materials such as SiGe, Ge or III-V materials. Among those materials, due to higher carrier mobility of Ge, it is promising as one of the candidates for high-performance devices with low-power and high-speed operation [1]. However several challenges still remain for the fabrication of Ge MOSFETs. For junction formation, it is difficult to form shallow N+/P junction in Ge due to the anomalous high diffusion coefficient of donor ions. On the other hand, forming shallow P+/N junction is relatively easy, however the high activation is difficult. To address these problems, some processes have been proposed such as aluminum doping [2], group-III metal doping [3] and optimization of Flash Lamp Annealing (FLA) [4]. In this study, we focused on the effect of oxygen remaining in the surface region of Ge substrate. Generally, a large amount of solid-solved oxygen is contained in Ge substrate. It is known that the oxygen inside Ge crystal acts as a Thermal Double Donor (TDD) [5]. TDD will inhibit the activation of acceptor ions in Ge and result in increase in the sheet resistance (Rs) of p+ diffusion layer formed into the surface region of the Ge substrate. In order to improve the activation, the Ge substrate is pre-heated at high temperature in the vacuum chamber before ion implantation to control the oxygen concentration in the surface region. Oxygen atoms in the Ge substrate can easily out-diffuse at the initial stage of ion implantation. Furthermore implantation is carried out at relatively low temperature to avoid TED of boron. In this paper, we report the results of BF 2 implantation into Ge substrate with pre-heating process.

In recent years Solid Source Doping (SSD) has been considered as a viable option in fabricating advanced CMOS devices [1], especially for forming shallow and highly doped junctions for source drain extensions (SDE) while minimizing the damage to the devices [2]. Current scaled devices require diffusion control in the nanometer range in order to form shallow SDEs using SSD. Additionally, high doping concentrations are needed to lower the resistivity (see Fig. 1).

We demonstrated the formation of ultra-shallow n+/p junctions in Si using an arsenic-doped Sol-Gel Coating (SGC) (Tokyo Ohka Kogyo Co., Ltd.) [1] and Flash Lamp Annealing (FLA). A high arsenic dopant concentration of 1.2×1020atoms/cm3 (Xj=9.0nm, Rs= 1203ohms/sq.) with a good junction profile (2.2nm/decade) was realized with 1.4ms FLA. These results indicate that this technique can be used for conformal doping of the Source/Drain Extensions (SDE) in sub-10nm FinFETs fabricated using advanced 3D device engineering.

A new millisecond, flash lamp annealing (FLA) tool has been developed. Building on the current tool's wide range of annealing times and temperatures, the new FLA tool is equipped with an ambient control system that can establish a reduced pressure and/or an NH3 reactive-gas ambient. These features have an advantage in gate stack anneals compared to conventional second order annealing: FLA prevents deactivation of dopants in gate-last processes, further densifies the HfO2 layer and the IL, and enables nitridation of the HfO2 layer while avoiding N diffusion to the Si substrate. Moreover, the electrical properties using MOSCAPs processed by FLA show prominent improvements in the EOT and gate leakage current. A positive Vfb shift is also observed in MOSCAPs using FLA. These results show that FLA using NH3 is a promising process for sub 10nm generation gate stack anneals.

Conductive paste degrades the solar cell performance due to the metallization. Silver crystallites at the interface may shunt the p-n junction, which degrades the cell performance. Besides, it is conceivable that glass frit itself should not effectively damage silicon, but there is no clear evidence for the proof. In this study, the “floating contact method” proposed by R. Hoenig is used to evaluate the effects of glass frit by making the floating contacts with the glass frit. It is conclude that glass frit itself causes shunts and increases the saturation current, which corresponds carrier recombination beneath the glass frit contacts.

N-type crystalline silicon can be expected to achieve high-efficiency compared with p-type one. For the n-type solar cells, silver/aluminum paste has been used as metallization for p+ emitter, which induces loss in open circuit voltage (V oc ) of the cells. In this study, the effects of glass frit in the metallization paste on the loss in V oc are investigated, dividing the respective effects of the glass frit and the aluminum in the paste. The glass frit in the metallization paste decreases the V oc due to shunting of p-n junction and increasing recombination current, even if the paste contains no aluminum.

In this paper, we report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths formed for the n+/p and p+/n junctions were 9.5 nm and 10.7 nm with sheet resistances of 620 ohms/sq. and 414 ohms/sq., respectively. Additionally, by reducing knocked-on oxygen during ion implantation, the sheet resistance was decreased by 5 to 15%. The lowest sheet resistance was 235 ohms/sq. with a junction depth of 21.5 nm in the n+/p Ge. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices.

It was found that critical dimensions of high-k/metal gates obey the multivariate linear approximation with the precision of 3σ=±0.86nm, whose explanatory variables are amounts of metal compounds remaining on the plasma reactor walls. To measure their amounts, the authors assumed they are proportional to amounts of atoms sputtered out by Ar plasma and falling onto a Si wafers placed on a wafer stage. In this study, effects of metal compounds of W, Ti, Ta, and Hf, which are used to construct full-metal/high-k gates, were measured. It was found that Ti and Ta compounds dominate the fluctuation of critical dimensions and the dependency of their amount on wafer numbers being etched obeys a simple difference equation. From these results, they can estimate and minimize the fluctuations of critical dimensions in mass fabrications.

Film thicknesses of W, TiN, and TaSiN in a full-metal gate stack with photoresist masks were measured in real time during plasma etching with an in situ thickness monitor. The accuracy of such measurement was approximately ±1 nm. The monitor functions on the basis of the interference of plasma optical emission, reflected from the surface and base of the film. Although W and TiN have large absorption indexes, their thicknesses were more accurately measured when they became thinner. In particular, W thickness was estimated more accurately when it was smaller than approximately 10 nm.

We have investigated the time dependent dielectric breakdown (TDDB) for a high-k/metal gate p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) under inversion stress. We have found that electrons, injected from the cathode, are minority carriers in the gate leakage current and play an important role in determining TDDB lifetime and that the existence of oxygen vacancies in HfSiON, decide the electron current mechanism in HfSiON. Since electrons from the cathode flow as a tunneling current with the effective barrier height determined by the energy level of the oxygen vacancies in the HfSiON, electron current is strongly dependent on the effective work function of the metal gate. That implies that a higher work function should be effective to suppress of electron current, due to the elevated barrier height for electrons. Therefore, the formation of a high work function metal gate is essential, not only for low threshold voltage of pMOSFETs but also to achieve long TDDB lifetimes.

We have investigated the impacts of the nitrogen content in a TaSiNx metal gate on the performance of metal/HfSiON n-type field-effect transistors (FETs). To obtain a low threshold voltage and low electrode resistance, low nitrogen concentration in TaSiNx is preferable. However, the use of a TaSi gate ([N] = 0%) causes the degradation of HfSiON dielectric characteristics such as an increase in leakage current under gate negative bias, positive-bias temperature instability lifetime degradation, time-dependent dielectric breakdown lifetime degradation, and reduction of the electron mobility. Then, a low-nitrogen-concentration TaSiN ([N] = 20%) gate shows the highest electron mobility, excellent reliability characteristics, and low threshold voltage.

RuO2 films were investigated as a work-function-determining metal in metal/high-k gate stacks required for scaled complementary metal–oxide–semiconductor (CMOS) devices. After a low-thermal-budget processing below 400 °C, RuO2 on HfSiON exhibits a high effective work function of about 5.5 eV, which is applicable in p-channel field-effect transistors. However, RuO2 is easily reduced to Ru metal in metal/high-k gate stacks by annealing above 400 °C. Consequently, the high effective work function is unintentionally lowered. This is because RuO2 is thermodynamically unstable when in contact with W and polycrystalline silicon, which are both common components of a metal gate electrode structure. The insertion of TiN and TaN between RuO2 and W does not suppress the reduction. It is concluded that RuO2 is difficult to employ as a metal gate in metal/high-k gate stacks.

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (VTH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low VTH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of VTH roll-offs and Ion-Ioff's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

Methods of improving Fermi-level pinning of pure metal gate electrodes on Hf-based high-k dielectrics have been investigated. The pinning phenomenon is a crucial problem, resulting in an unintentional threshold voltage increase in p-MOSFETs when applying pure metal gate electrodes such as Ru and TiN in Hf-based high-k CMOS. After systematic investigation of the relation between oxygen vacancies in Hf-based high-k dielectrics and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. It is necessary to modulate the stable pinning energy position of Hf-based high-k dielectrics in p-MOSFETs in order to obtain thin EOTs in the gate-first process.

Vacancy-type defects in MOSFET structures fabricated with high-k (HfSiON) gate dielectrics were studied by monogenetic positron beams. An expansion of open volumes in HfSiON fabricated on Si substrates using atomic layer deposition technique was observed with increasing nitrogen concentration. This fact was discussed in terms of a role of nitrogen in Hf-related oxide using results obtained by first-principles calculation and XPS. MOSFETs fabricated by F-channel implantation technique were also characterized. The major defect species which causes the Vth shift of MOSFETs was identified as vacancy-fluorine complexes (such as V3F2) locate in channel regions of Si substrates. The preset work suggests that positron annihilation can be used to detect microscopic defects in MOSFETs, and it is a useful tool for determining process parameters for MOSFET fabrications with high-k gate dielectrics.

The peeling of an impurity-doped NiSi film was investigated. We studied silicidation in detail and showed that its procedure varies depending on the doping site and dopant species used. The uneven crystal growth of NiSi causes the local consumption of polycrystalline silicon; thus voids form at the film interface NiSi/SiO2. These voids lead to film peeling. We also determined why the local consumption of polycrystalline silicon occurs. From the data we obtained, impurity may play a role in the local consumption of polycrystalline silicon.

In this paper, we describe multiple-stressor technology (MST) for high-performance 45-nm-node devices. The combination of two or more stressors, namely, polygate stressor (PGS)/tensile stress liner (SL) for n-channel field-effect transistor (NFET), and embedded SiGe/compressive SL for p-channel field-effect transistor (PFET), is integrated into complementary metal–oxide–semiconductor (CMOS) process and its potential for device performance enhancement is investigated. Moreover, the issues of MST are also discussed from the viewpoint of variations in device characteristics under an extremely high channel strain, which are not pronounced in the previous technology with its relatively low strains.

We demonstrate the formation of n+/p ultra-shallow junctions in Ge using Flash Lamp Annealing (FLA). With FLA both shallow junctions and high activation can be achieved, for example, a sheet resistance of 400 ohms/sq with a junction depth of 20 nm. The shallowest junction depth was 17 nm with a sheet resistance of 493 ohms/sq. In addition, by varying the FLA conditions, i.e., the temperature and annealing time in the millisecond range, diffusion lengths of less than 30 nm can be controlled with a precision of 1nm. These results indicate that FLA has great potential for forming ultra-shallow n+/p junctions in Ge devices.

In this paper, the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-MOSFETs was directly evaluated. Using scanning tunneling microscopy (STM), it was clearly observed that the roughness of extension edges induced by gate LER strongly depended on the implanted dose, pockets, and coimplantations. Impurity diffusion suppressed by a nitrogen (N) coimplant enhanced the roughness of the extension edges, which caused fluctuations in the device performance. The expected effect based on the carrier profiles measured by STM of the N coimplant on the electrical performance of the n-MOSFETs was verified

In order to improve the NBTI of pMOSFETs with ultra-thin HfSiON gate dielectrics, a novel plasma nitridation process has been developed. Inclusion of hydrogen in the plasma nitridation ambient brings about an increased NBTI lifetime of about half an order of magnitude. The improvement is due to the suppression of bulk hole traps, presumably originating from the Hf-N bond. Hydrogen in the plasma ambient is thought to prevent the formation of additional Hf-N bonds during post- nitridation annealing.

We have directly measured the effect of the bottom shape in the offset spacer on the two-dimensional (2-D) carrier profiles of the sub-50 nm p-metal oxide semiconductor field-effect transistors (MOSFETs). It has been observed that the doping profile of the Sb pocket implanted with a high angle tilt is very sensitive to the bottom shape of the notched offset spacer. It has been confirmed that the Sb pocket deeply implanted leads to the decrease of 2 nm in the average overlap length of the extension region at a depth of 5 nm when the bottom shape is slightly upped at the notched offset spacer. The increased effective channel length is considered to enhance the dependence of the threshold voltage on the body bias voltage. Moreover, it is considered from the measured carrier profiles that the reduction in carrier concentration in the top channel region lowers the threshold voltage.

A decaborane implantation system has been developed. The maximum beam current achieved at a wafer is 30 μA at 5 keV with the divergence less than 0.4°, which corresponds to the equivalent 500 eV–300 μA boron monomer implantation without an energy contamination. As-implanted secondary ion mass spectroscopy (SIMS) profile of the decaborane implanted at the equivalent energy 500 eV shows the steeper and shallower profile than that of the boron implanted. The result of R s – X j proves the higher activation with shallower junction depth. These advantages possibly arise from the self-amorphization layer by the decaborane implantation.

This paper presents an analysis of noise occurrence at the 7th main bearing of an inline six cylinder diesel engine. From experimental results of the engine, it seems that cavitation in the bearing oil film is a major factor for this noise, and the noise occurs with a combination of the following conditions; (1) cavitation exists in oil film at the main bearing, (2) main journal is unstable and (3) excitation force acts at this moment. This assumption is analyzed using engine vibration analysis, EHL analysis and stability analysis. The results agree with the condition of the noise occurrence.

After discovering that the annealing-time dependence of the flatband voltage shifts of a p/sup +/-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M/sub 2/, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p/sup +/-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO/sub 2/.

Aluminum-added silver paste (Ag/Al paste) has been used for p+ emitter of n-type solar cells. The electrical losses due to shunting and recombination caused by the paste in the cells have been reported to originate from huge metallic spikes due to the aluminum. However, whether the aluminum actually induces the losses has not been clarified yet. In this study, the "floating contact method" is applied to aluminum-free silver (Al-free Ag) paste to investigate the effects of aluminum extraction from the Ag/Al paste and to understand how the aluminum principally induces the losses for the p+ emitter. Furthermore, the interfacial morphology between the Al-free Ag paste and p-type silicon is investigated. The Ag paste itself creates tiny crystallites for the p+ emitter, resulting in shunting and recombination. The result indicates that the aluminum addition to Ag paste is not the main reason for the electrical losses in the n-type solar cells.

We demonstrated that ion-implantation damage in gate SiO2-enhanced boron penetration in p-channel metal–oxide–semiconductor devices, easily enhances boron diffusion in SiO2 by ten times or more. This article describes the effectiveness of using high-temperature annealing above 1000 °C on damaged samples to suppress boron penetration in samples damaged by ion implantation. We also performed an electron spin resonance measurement to examine the damage recovery.

We studied the diffusion of dopant impurities, that is, ion-implanted boron, phosphorous, arsenic, and antimony in SiO 2 and determined the diffusivity of the impurities in SiO 2 using secondary ion mass spectrometry and a process simulator. We also revealed anomalous diffusion of the dopant impurities in SiO 2 .