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With the expansion of Internet of Things (IoT) by artificial intelligence (AI), there is a strong demand for higher performance, higher intelligence, and lower cost in endpoint devices for crossover area located at the boundary between high-end micro controller unit (MCU) area and low-end micro processor unit (MPU) area, such as home automation, machine vision, robotics, and so on. This article presents a 40-nm embedded split-gate MONOS (SG-MONOS) flash macro with optimized memory array architecture and charge-assisted offset cancellation sense amplifier (CAOC-SA), which achieve high-speed random read operation of 200 MHz and high density of 7.91 Mb/mm2 suitable for crossover devices. [ABSTRACT FROM AUTHOR]

First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from -40^\circ\ C to 170^\circ\ C as demanded strongly in automotive uses. Much attention has been paid to the degradation of the reliability characteristics along with the process shrinkage. Temperature-adjusted word-line overdrive scheme improves random read access frequency by 15% and realizes both of 6.4 GB/s read throughput by 200 MHz no-wait random access of code flash macros and more than ten times longer TDDB lifetime of WL drivers. Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million rewrite cycles. Source-side injection (SSI) program with negative back-bias voltage achieves 63% reduction of program pulse time and, consequently, realizes 2.0 MB/s write throughput of code flash macros. A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and peak power of EMI noise is reduced by 19 dB. [ABSTRACT FROM PUBLISHER]

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-µm logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 µW owing to the hierarchical power supply and SSR. The macro size is 4.59 mm². The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process. [ABSTRACT FROM AUTHOR]