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A single-phase high power electronics package is designed and developed in this paper. The developed power package achieves a significant thermal performance improvement compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. First, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid-cooled heat sink attached to the bottom side of the AMB substrate is shortened. Hence, the thermal performance of the package is improved. Moreover, customized copper clips are introduced as the electrical interconnections between the SiC chips and the top metal layer of the substrate at the same level, and the top surface of the power package remain flat. As such another heat sink can be added to the top side of the package to further improve the thermal performance of the power package through the double-side cooling (DSC) scheme. The simulation results show that the junction-to-case thermal resistance (Theta JC) of the optimized power package is about 50% less than the Theta JC of the conventional wire-bonded power package with the same package size and the same power rate. Further applying the DSC scheme to the proposed power package, which is not suitable to the conventional wire-bonded power package, the Theta JC of the proposed power package reduces another 20%. In addition, the effects of the core layer (i.e., material and thickness) and the metal layer (i.e., materials and thicknesses) of the AMB substrate, as well as the die attach (i.e., material and thickness) on the Theta JC of the proposed power package are investigated systematically. As such the thermal performance of the power inverter package is further elaborated. Finally, the thermally enhanced power package is fabricated and assembled. Thermal characterization has been conducted, and the thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other.

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.

For mm-wave application, the size of package with antenna becomes very small, which poses critical challenge for heat dissipation issue. The function demand for high performance and higher duty-cycled condition makes the thermal issue even more severe. In this work, thermal performance investigation has been performed at package level and modules level, and thermal solutions have been designed for performance improvement. Thermal performance of the package is firstly evaluated at package level. For the module performance analysis, due to multiple packages are included, various heating conditions are studied to provide a comprehensive thermal analysis. The effects of thermal via in PCB, cavity filling blocks, and bottom heat spreader on module heat dissipation capability have been studied. Effective solutions have been obtained to maintain all chips safe even under worst case condition. Module level thermal solution is able to achieve ∼12% further performance improvement for all working modes. The conclusions and results obtained have been used in AiP module co-design for automotive radar.

A Finite Element Analysis (FEA) modelling study on solder joint fatigue life assessment under thermal cycling conditions for two High Density (HD) Fan Out Wafer Level Packaging (FOWLP) packages is presented in this paper. Package designs and material properties of FOWLP packaging materials such as photo-dielectric and epoxy molding compound are studied. Unlike the conventional numerical parametric study, this study adopts both Ansys Mechanical and the statistical analysis tool Minitab to analyze the modelling results. Facilitated by the statistical tool, the solder joint Thermal Cycling on Board (TCoB) fatigue life prediction formulas have been derived. For any parameters within the data ranges prescribed in Design-of-Experiment (DOE) table, solder joint fatigue life can be quickly calculated by using the derived prediction equations. Furthermore, critical factors that significantly affect solder joint fatigue life are identified by the statistical tool. Hence, the novel numerical methodology presented in this paper, which integrates the FEA modelling tool and the statistical tool, is able to enhance the efficiency of the Design Technology Co-Optimization (DTCO) process for solder joint TCoB fatigue life assessment.

One of the challenges in processing Fan Out Wafer Level Package is the warpage of the Molded Wafer. Some of the fabrication processes such as lithography, coating, etching, and plating could not process wafer with high warpage. Therefore, the molded wafer should have as low a warpage magnitude as possible. In this paper, we study the warpage behavior of the molded wafer with different die to mold ratio. Further work is done on evaluating the impact of different chuck temperatures during the debonding process for the wafer with the highest warpage. The debonding process involved removing the molded wafer from the metal carriers, removing the thermal release tape from the molded wafer, and subjecting the molded wafer to series of thermal treatments to reduce the final warpage of the molded wafer.

Antenna-in-Package (AiP) technology has emerged as the mainstream advanced package integrated with antenna and transceiver die for automotive radar application. In this work, thermal performance investigation has been performed on three types of AiP. The effects of underfill material, PCB, RDL, and solder array on package thermal performance has been studied, as well as the combined effects of multiple factors. According to the thermal affecting factors analysis, thermal performance improvement solution has been suggested. All 3 types of package have been analyzed. By using the improvement solution obtained from this analysis, the maximum chip temperature rise can be reduced by ∼20%, and the package internal resistance can be reduced by ∼15%.

The Fan-out wafer-level packaging technology is an integrated circuit technology as well as an enhancement of standard wafer-level packaging (WLP) solutions. This technology is an attractive packaging approach for mobile applications and heterogeneous integration. It allows better electrical performance, low form factor and at relatively low cost as compared to wafer to wafer stacking or 3D stacked bonding. Furthermore, as the industry moving towards higher density and higher-bandwidth chip to chip interconnections, the application of Package on Package technology offers a solution for applications processors and mobile applications with better thermal and electrical performance. One of the significant advantages of package-on-package FOWLP is the ability of stacking 2 different packages to achieve multi-functionality. However, the overall package has to maintain a low profile for thin portable applications. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is after singulation. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is $15 \times 15\ \mathbf{mm}^{2}$ after singulation. Detailed process parameters on flux printing process parameters such as the printing speed and printing gap coupled with ball placement speed, ball dispense gap and ball head moving direction needs to be evaluated to achieve robust wafer level solderball placement process with good flux printing and good ball placement process yield.

Mobile application or appliance demands multi-functions, high speed, light or small form factor and low cost. One of the common approaches to meet all these requirement is put one package over another package. This approach is commonly known as Package on Package. Package on Package can be realized by assembled the package either through the use of organic substrate, or fan-out wafer level package. The top package is stacked on top of the bottom package using solder balls or copper pillars.In this paper, we used fan-out wafer level package’s approach to demonstrate the vertically integrated package on package. The top and bottom package are merged together using fan-out wafer level approach during the assembly process to form Vertically Integrated Package on Package.

In this paper, failure mode and mechanism analysis on Cu wire bond and bond pad reliability for Cu/low-k chip are investigated through wire pull test and finite-element analysis (FEA). The wire pull test has been carried out for the bonded Cu wires with changing pull position to reveal different failure modes. Failed load is monitored and failure mode is analyzed for different wire pull test conditions. It is observed that the pull position influences failed pull force and failure mode. Failure modes include broken wire neck and wire wedge, ball lift, and pad peel and the failed force decreases with a changing pull location from the ball bond toward the wedge bond. FEA simulation is performed to help further understand failure mechanism and establish failure criteria. Finally, failure mechanism and criteria are presented for different failure modes and materials. In addition, the influence of wire loop height is also studied.

Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications. Package-on-Package has the benefit of a mini packaging size with multi-functionality by stacking two different packs. However, an ordinary Printed circuit board substrate Package on Package has a weak point to meet the now low profile necessary of high-performance in the thin portable application. To overcome this weak point, the package has been introduced to the market by Fan Out Wafer Level, and this structure of the package allows I/O to be within the device surface and expand through the combination of form so that they can be accommodated more FOWLP. Ultra-thin Fan-out PoP was developed using RDL-first process flow. The developed Fan-out PoP has a package size of 15 x 15 mm2 and thickness of 800 µm, and it consists of three embedded chips. The bottom package consists of a 10 x 10 mm2 processor chip assembled to under bump metallization (UBM) of the bottom RDL layers. Vertical wire-bonds are integrated into the bottom package to act as vertical through mold interconnect (TMI) to the top RDL layers. The top package consist of two 7 x 11 mm2 silicon chips assembled laterally on top of the bottom package and connected to the top RDL layer with low-loop wire-bonds. The top chips were encapsulated in epoxy mold compound to form an integrated PoP. RDL-first integration flow was used to fabricate the fan-out package whereby RDL, molding and chips assembly processes were performed on a carrier wafer to overcome warpage associated with conventional Mold-first process. The ultra-thin Fan-out PoP samples pass the reliability include the MST level 3, drop impact test and the Thermal Cycling. It also provides good thermal performance on packaging level and system level applied in mobile device.

In this paper, a half-bridge leg single phase power package with SiC based MOSFETs (metal-oxide semiconductor field-effect transistors) on a AMB (active metal brazing) substrate was developed. The developed power package consists of a AMB substrate with specially designed cavities, four high power rated SiC chips, three types of customized copper clips forming the source and gate interconnects. High temperature die attach/solder material for the chip, substrate and copper clip bonding, and high temperature endurable encapsulation mould compound (EMC) for cavity and gap filling have been evaluated. The fabricated power packages were undergone the specified reliability assessments, i.e. unbiased highly accelerated stress test (HAST) test, thermal cycling (TC) test (-40~200°C), High temperature storage (HTS) test at 250oC and power cycling test (ΔT=150°C). 5 out of 5 samples passed the standard unbiased HAST test and HTS test for 500 hours. 4 out of 5 samples passed the TC test for 1000 cycles and 3 out of 5 samples passed the power cycling test for 10000 cycles. Electrical open failures were detected between clip 1, traces on the substrate and gate pads of the SiC chips. Interconnects between clip 2/3 and source pads of the SiC chips show good connections. Delamination between the clip 1 and sintered Ag were observed on the failed samples by the cross section failure analysis which is the potential root causes of electrical failure.

The continuous requirements of package miniaturization in the demand of mobile application market have shown the increase in demand of many FOWLP packaging [1]. The applications of FOWLP has many advantages including shorter interconnection, lower heat resistance, better electrical efficiency and smaller package form factor [2].The work presented in this paper describes the reconfigured wafer approach in fan-out wafer level technology that allows multiple dies with high solder interconnect to package using the molded interposer for FOWLP technology. In this work, we presented some of the work done prior to the flip chip bonding process and the different approaches to resolve some of the process issues encountered in the assembly process for 3 test dies with high I/Os onto a fan-out mold interposer. The 1st test die is the 15x15mm ASIC die with 21472 I/Os and the remaining 2 dies are the 7x7mm HBM dies with 4942 I/Os. Both the ASIC and HBM dies have a minimum bump pitch at 55 μ m. The 12 inch through molded interposer wafer is singulated into individual interposer prior to the flip chip attachment process.The package warpage remains the main concern in the through mold interposer assembly. To minimize interposer warpage, a metal stiffener was attached to the molded interposer. Results shows the attachment of the metal stiffener helps to reduce the package warpage. In addition, a thinner die thickness of 150 μ m helps to reduce the overall molded interposer package‘s warpage after assembly compared to a die thickness of 500 μ m. Cross-section analysis was done to inspect the solderjoint shape at 150 μ m and 500 μ m die thickness. Further optimized thermocompression bonding process and capillary underfill process helps to ensure good solderjoint interconnection and no underfill voids for a robust Fine pitch interconnect Fan-out WLP assembly.

A Wafer Level Chip Scale Packaging (WLCSP) solution with CuPd wire in epoxy mold compound (EMC) as through mold interconnection (TMI) was proposed for the capacitive MEMS such as accelerometer packaging. The size of fabricated WLCSP is 2 mm × 2 mm × 0.83 mm. Silicon cap was designed as 1 mm × 2 mm × 0.1 mm. Device wafer and cap wafer was bonded with wafer level Al/Ge eutectic bonding process. Vertical CuPd wire with diameter of 2 mils embedded in the EMC was used as the TMI. Dummy ASIC die with the size of 1 mm × 1 mm × 0.15 mm can be mounted on the UBM above the RDL of the WLCSP with micro-bumps. MSL1, -40 oC to 125 oC thermal cycling (TC), unbiased highly accelerated stress test (HAST) and 150 oC high temperature storage (HST) testing was conducted on the fabricated dummy test vehicle samples. Testing results show that the fabricated test vehicle can pass the tests without electrical failure. The WLCSP with CuPd wire in EMC as TMI has been successfully demonstrated, which provides the confidence for the next step fabrication of WLCSP with functional accelerometer.

A single phase high power package is designed and developed in this study. The developed power package achieves significant thermal performance improvement as compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. Firstly, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid cooled heat sink attached to the bottom side of AMB substrate is shortened. Moreover, customized copper clips are introduced as the interconnections between the SiC chips and top metal layer of the substrate in the same level, and the top surface of the power package remains flat. As such another heat sink can be added to the top side of the package to improve the power package thermal performance further by implementing this double side cooling (DSC) Scheme. Results of the modeling and simulation show that the proposed package junction to case thermal resistance is ~50% less than the junction to case thermal resistance of the conventional wire bonded power package with same size and same power rate. Further utilizing two heat sinks on the both sides of the proposed power package which is not suitable to the conventional wire bonded power package, the junction to case thermal resistance of the proposed power package reduces another 20%. In addition, the effects of the core and metal layers of the AMB substrate on the thermal resistance of the proposed power package are investigated systematically. Finally, the thermally optimized power package is fabricated and assembled. Thermal characterization has been conducted and thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other.

Current-induced failures in fine pitch Sn microbump with Cu pillar have been investigated under a current density of $3.2\times 10^{4}$ A/cm $^{2}$ and temperature of 150 °C. This process takes place in 2000 h of electromigration test. From the focused ion beam image and energy dispersive X-ray analysis, we observed the intermetallic compound formation, Kirkendall effect, and crack contributed to this failure. There are two stages of failure process for Cu pillar with microbump during current stressing. In the first stage, the whole Sn solder was transformed into intermetallic compound and Kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In the second stage, the Kirkendall voids coalesced into larger porosities then formed continual crack by current stressing, leading more bump resistance increase.

Drop test reliability of the 20 mm × 20 mm RDL-first FOWLP on bottom and 8 mm × 8 mm WLCSP on top for Package on Package (PoP) test vehicle was validated by the experimental testing in this paper. The results show that the built up PoP test vehicle can pass 30 times of drop impact test and some samples can pass 200 times drop impact test with the loading of 1500 G/0.5 ms. The failure mechanisms of Cu pad peeling off, cracking of dielectrics and Cu trace of the bottom RDL-first FOWLP and cracking on package corner solder joints of top WLCSP were identified by cross section observation. The peeling stress level on the solder joint and dielectrics layer were investigated by the dynamic explicit nonlinear drop impact simulation.

Cu ball bonding faces more challenges than Au ball bonding, for example, excessive deformation of the bond pad and damage of Cu/low-k structures, because of the much greater hardness of Cu free air balls. In this study, dynamic finite-element analysis (FEA) modeling with displacement control was developed to simulate the ball-bonding process. The three-dimensional (3D) FEA simulation results were confirmed by use of stress-measurement data, obtained by use of stress sensors built into the test chip. Stress comparison between two-dimensional (2D) and 3D FEA models showed the 2D plain strain model to be a reasonable and effective model for simulation of the ball-bonding process without loss of accuracy; it also saves computing resources. The 2D FEA model developed was then used in studies of a Cu/low-k chip to find ways of reducing Al bond pad deformation and stresses of low-k structures. The variables studied included Al pad properties, capillary geometry, bond pad design (Al pad thickness, Al pad coated with Ni layer), and the effect of ultrasonic bonding power.

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

This paper focuses on the 3-D numerical methodology development of wafer level compression molding. With its successful application in a two-die-package embedded wafer level encapsulation, flow patterns, velocity, and pressure distributions are compared for different die size and die thickness. The computed flow-induced forces indicate which zone has a high risk of die sliding. The simulated molten molding compound flow fronts are compared with actual molding short shot samples. The key advantage of this numerical study is that it helps detect the molding defects quickly and improve moldability problems efficiently, in order to reduce manufacturing cost and design cycle time.

A ball bonding process in wire bonding generally involves impact followed by ultrasonic (US) bonding prior to wedge bonding. During the ball bonding process, the impact force flattening the free-air ball introduces significant localized out-of-plane compressive stress on the pad and the low-k structure beneath. The subsequent process of US bonding induces in-plane and shear stresses to the structure. High induced stress during bonding is not desirable, as it may lead to pad damage or cratering of the silicon structure. In this paper, we report on studies conducted on using four piezoresistive sensors embedded underneath the center of the bond pad for the evaluation of in-plane and out-of-plane stresses, which covers both the impact and US stages during the ball bonding process. Different levels of impact force, bond force, bonding duration, and US power are investigated using gold wire bonding for feasibility and sensitivity studies of the stress sensors. Fast Fourier transform (FFT) and inverse FFT are used for noise filtering and to isolate the US signal yielding a continuous output signal from the in situ measurement of contact and US stages during the ball bonding process. It is found that the stress sensors are sensible to capture different impact force, bond force, bonding duration, and US power.

RDL first FOWLP with the advantages reducing die shift and wafer level warpage during the fabrication process has been developed. The drop impact reliability for the large size (20 mm×20 mm) RDL first FOWLP is one major concern for the mobile applications. Under drop test loading, crack and delamination failures may happen to the dielectrics layer and solder joints. In this paper, reliability of 20 mm×20 mm RDL fist FOWLP was investigated by the drop impact test and dynamic simulation. The drop impact tests under the loading of 1500 g/0.5 ms were conducted for the RDL fist FOWLP. The drop impact reliability of RDL first FOWLP was validated by the drop impact tests. The failure analysis by doing the cross section and SEM observation was conducted to initial failure sample in order to find out the failure mechanisms. The stress behavior of the solder joints and RDL were investigated by the dynamic drop impact simulation. The effects of the delamination on the stress level on the dielectrics layer under the solder joints was identified by the simulation.

Through mold interconnects (TMI) is a key enabler for fan-out wafer level packaging (FOWLP) for 3D integration. Three different types of TMI have been developed for both mold-first and RDL-first fabrication flow. The three types of TMI consist of laser drilled vias, vertical wire-bonds and Cu pillars interconnect. The process flow and fabrication results of each TMI will be presented in this paper.

In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout induces large stress and deflection in the lower die under the die-stacking process. Three-point bend tests were conducted to determine the die strength. Die-stacking experiments were also carried out. The experimental results show that the bottom die cracks when the middle die is stacked and the middle die cracks when the top die is stacked even with a small stacking force. Consistent results have been obtained among FE simulation, die strength bend test, and die-stacking experiments. An optimal bump layout design is proposed, which adds some dummy bumps on the central area of the die to support the bending force induced by the die-stacking process. The optimal design significantly reduces the die stress level and deflection. Finally, a successful die-stacking process is achieved even using a larger stacking force.

This paper presents the effect of back grinding on the mechanical properties of the active side of the multilayered low-k stacked die. Low-k stacked wafers were thinned to four different thicknesses of 500, 300, 150, and 75 μm by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed on both the normal (no back grinding) and back grinded samples to analyze the failure strength, modulus, hardness and adhesive/cohesive strength of the low-k stack. It is found that the back grinding process enhances the mechanical integrity of low-k stack as the back grinded low-k stack exhibited improved fracture load and cohesive and/or adhesive strength as compared to the normal low-k stack. The transmission electron microscopy cross-section analysis showed that the interfaces in the low-k stack of normal sample are wavy, whereas the interfaces in the grinded low-k stack samples are even, especially at the Black Diamond (BD), low-k region. Significant densification of BD films was observed in the case of back grinded sample. Based on these results, it is believed that the thermo-mechanical stresses applied and/or generated during wafer back grinding process affect the microstructure of low-k stack and thus enhance the mechanical strength of the low-k stack.

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

Bump shear is widely used to characterize the interfacial strength of Cu/low-k structures. In this paper, the blanket low-k structure was used to evaluate the reliability and strength of Cu/low-k structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-k interfaces with different low-k structures, to understand the failure mechanism, and to improve low-k structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-k structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-k structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-k structure. An Sn-Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low-k structure reliability.

In the present study, we have investigated the thickness dependence of mechanical properties of the Black Diamond™ (SiOC:H, BD, Low-k) films, which are of great interest in current Cu/low-k Back End of the Line (BEOL) interconnect/packaging technologies. For this investigation the BD thin films of six different thicknesses 100, 300, 500, 700, 1,000 and 1,200 nm were deposited on the 8″ Si wafer by using plasma enhanced chemical vapor deposition (PECVD) technique. Nanoindentation and nanoscratch tests of the BD films were performed by using the Nano Indenter® XP (MTS Corp. USA). In nanoindentation testing of the BD films, significant differences in the elastic modulus of the BD films were observed. In nanoscratch testing, it is found that the critical load (Lc) and scratch width increases as the thickness of the film increases. Cross-sectional analysis of residual nanoindentation impressions was carried out using atomic force microscopy (AFM) to study the deformation behavior. The nanoindentation and nanoscratch responses of the BD thin films of six different thicknesses are different and they are expected mainly due to the molecular reorganization in thin/ultra thin films.

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.

This paper focuses on the packaging process and assembly and interlayer dielectrics (ILD) structural stability including mechanical simulation with polymer-encapsulation and redistribution process for 150-pitch Pb-free flip chip packaging of low-/Cu interconnects. Chemical vapor deposition (CVD) type low- test vehicles with four Cu layers were fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution (RDL) technology were applied using wafer integration technology to minimize the stress from the solder bump pad to low- ILD. This polymer encapsulated dicing line (PEDL) was introduced and the result of investigation discussed. Finite element method (FEM) mechanical simulations are performed for RDL approach, normal direct bumping, and PEDL. According to the results with shear loading, RDL approach showed less stress than that of direct bumping at the solder joint. Simulation indicated the die corner stress is reduced significantly on chip with PEDL as compared to that without PEDL. For copper postinterconnects, cost-effective and thick photoresist process was developed and optimized for electro Cu plating and solder was deposited on the top of Cu post. Bump shear test was carried out to evaluate the bump quality and failures were analyzed. After flip chip assembly with Cu/low- devices having via-chain and daisychain interconnects, various JEDEC standard reliability tests were carried out and failure analysis was performed.

In this paper, spin-on photoresists were evaluated to form ultra-thick photoresist mold for electroforming of 200 μm height Cu pillar structures with a diameter of 150 μm. Two photoresists materials of different exposure tone (positive & negative) were assessed. A double spin-coating process was required to achieve the required resist film thickness. The soft-bake, exposure and developing parameters were optimized to obtain suitable photoresist profile. Substrates with developed photoresists were subjected to electroplating process to test their chemical resistance A stepped EBR was implemented to overcome poor electrical contact with plating jig due to the thick edge bead. After Cu electroplating, the different materials were subjected to stripping solvent to assess their stripping performance.

Provide the sensor responses for various bonding power from 76 DAC to 200 DAC and use optical microscopy images, Current-Voltage curves and stress responds to find the regions of bondable and bond failures. When the bonding power increased, the stress magnitude of σx, σy and σz all increased. Good bonding could be achieved with bonding power less than 100 DAC. When bonding power is more than 100 DAC, bond failure or sensor damage could be occurred. The bond failure mechanisms include that under Al pad crack and Silicon cratering after wire bonding.

A test rig was developed to do high speed solder ball shear tests on a servohydraulic testing machine. Shear tests were conducted over a range of shear rates on eutectic tin–lead and lead-free solder balls that were mounted on a chip scale package (CSP) with a solder mask defined (SMD) ball grid array (BGA) configuration and on the Cu pads in a maskless printed wire board (PWB). The high speed ball shear test was found to induce a brittle solder/pad interface fracture that resembles the fracture in lead-free interconnects of board mounted microelectronic devices that have been subjected to mechanical shock. An approximate static analysis of the solder ball shear test has been developed that enables the plastic, fracture, and friction work to be separated. This analysis suggests that the specific work after maximum load obtained for low shear rate is closely related to the toughness of the solder. Provided the fracture was stable, the specific work after maximum load was relatively insensitive to shear rate suggesting that the solder toughness is also rate insensitive. The shear strength and total specific shear work all increase with shear rate.

In this paper, the fabrication process and results of 2.5D through silicon interposer (TSI) package using polymer based RDL and chip-on-wafer (CoW) stacking-first approach is presented. The through silicon interposer is fabricated on a 300 mm silicon substrate with Cu filled vias of aspect ratio of 1:10. Fine-pitch Cu RDL using semi-additive process and polymer based dielectric is used to form the 3 layer of rerouting layer on front-side. Chips with micro-bumps are flip chip assembled onto the under bump metallization (UBM) of the 12 inch interposer substrate using thermal compression bonding via chip-on-wafer (CoW) format on the thick interposer substrate A wafer level molding process is used to form the over-mold encapulation over the assembled chips. The over-mold encapsulation is mechanically thinned down to reduce the warpage of the molded interposer and temporary bonded to a silicon carrier. Mechanical-grinding and chemical mechanical polishing (CMP) is used to expose the Cu vias from the backside. Cu-RDL process is used to form the backside re-routing layer and UBM for solder bumps. The completed interposer wafer is then diced into singulated packages for assembled to printed circuit board (PCB).

The use of flip-chip technology in packaging interconnects is becoming more important due to its better electrical performance, smaller form factor packages, and higher interconnect density than wire bonded packages. Flip-chip soldering has been the mainstream flip-chip technology. However, the move towards fine pitch Cu pillar flip chip packaging with fine pad bond pitch has driven the investigation of Sn plated bumps on Cu pillar encapsulated with wafer level underfill as a potential alternative [1]. As the pitch of the electrical interconnections decreases and chip size increases, it is more difficult to develop high through-put processes using conventional capillary flow underfills. A WLUF process eliminates the time required to dispense conventional underfill to every chip and for capillary flow [2]. Fillers are used in underfill materials to decrease the coefficient of thermal expansion (CTE) which has the effect of reducing package stresses, and helping to achieve better reliability performance. However, in the case of WLUF with high filler content, it is very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints and void-free underfill as the epoxy based WLUF can cure early, below the Pb-free solder melting temperature, and become trapped between flip chip bumps and substrate solder pads. Also, the high process temperature of Pb-free solder can cause a large amount of voids to form within the WLUF material during the solder joining cycle [3-4]. In the paper, a WLNCF with 40% fillers was laminated onto 8 inch wafer containing Cu pillar post with Sn solder bumps by spin coating. The wafer was diced into chips. A chip was aligned and joined to a substrate with an optimized heating and cooling cycle. The effects of the bonding parameters and bonding temperature profile on the fine pitch flip chip assembly on solder wetting, solder joint shape and WLNCF voids are addressed in this paper. The main challenge for the fine pitch flip chip assembly was to assemble a fine pitch Cu pillar assembly onto an organic substrate while ensuring good solder wetting, good bonding placement accuracy, minimum solder joint voids, good fillet coverage and no wafer level underfill trapped between the solder and substrate bond pad after thermocompression bonding. In addition, wafer level underfill lamination uniformity and voids after lamination and B-stage cure were inspected. Wafer dicing evaluation was also performed to ensure no debris or particles adhering to the WL-NCF during dicing. No peeling or delamination of the WL-NCF was observed after dicing. The impact of these various factors on the stacked die assembly is discussed in this paper.

Through mold via (TMV) provides a potential solution for the 3D microelectronic packaging. The reliability of the TMV is one of the major concerns during its applications. In this paper, the reliability of the TMV structure used for the embedded wafer level packaging (eWLP) was studied by the finite element simulation under the moisture 85°C/85RH, reflow and thermal cycling loading conditions. Fracture mechanics was used to calculate the strain energy release rate of the delamination between the plating copper and molding compound. The effects of the material properties and structure parameters were examined by the simulation results. The efforts can provide some guidelines for the reliability design of the 3D microelectronic packaging with TMVs.

In this paper, a different type of through mold interconnects, known as Via-in-Mold (ViM) was developed for embedded wafer level package (EMWLP) to enable 3D stacking application. Via in Mold (ViM) interconnects are blind vias laser drilled into the mold compound with Cu plated sidewall metallization forming the electrical connection between top and bottom sides. The two main challenges faced in the development of the ViM are: laser formation of the blind vias and Cu plating along via sidewall. Mold compound is a composite material made up of inorganic fillers and epoxy resin. In order to improve the packing density of the mold composite, a wide distribution of filler particle size is often used. This resulted in a non-uniform material which is very difficult to be laser drilled. ANd:YAG laser of a spot size of 20 um was used to drill blind vias and the laser drilling process was optimized to achieve consistent blind vias of ~100 um top diameter and 200 um depth stopping on the front side Cu pads. The design of the front side Cu pads plays a very important aspect during the laser drilling. Fabrication result shows that smaller Cu pads structures tend to delaminated during the laser drilling as they are unable to dissipate the heat generated by the laser source during the via formation process. Electroless Cu plating process was used to deposit the Cu seed layer along the blind via sidewall. The electroless process was optimized to achieve better sidewall coverage in the blind via. From the fabricated test vehicle, the via-chains electrical resistance was measured to extract the resistance of a single ViM. From the electrical resistance measurement, the resistance for a single ViM chain is ~0.095 Ω.