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Minaei, Shahram (Dogus Author) In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.

Minaei, Shahram (Dogus Author) The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 μm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm2 and the power consumption is about 436 μW.

Minaei, Shahram (Dogus Author) In this paper, new analog memristor emulator circuits based on current backward transconductance amplifier (CBTA) and passive elements are proposed. They emulate both types of memristor (incremental and decremental) just by interchanging the CBTA output terminals. It uses only one CBTA, two resistors, one capacitor and one multiplier emulating grounded memristor. They consist of less CMOS transistors and have wider output ranges compared to other designed emulator circuits. The CMOS implementation of the CBTA using 0.18 ttm level-7 TSMC CMOS technology parameters is also proposed. It uses 23 CMOS transistors operating with the +/- 0.9 V DC supply voltage. Theoretical derivations and related results are validated using SPICE simulations.

Minaei, Shahram (Dogus Author) In this study, we present a new NMOS implementation of differential difference stage containing only eight transistors. The introduced new differential difference stage has high input impedance and low output impedance; accordingly, it can be directly cascaded without loading effect. In addition, a detailed study on the input referred noise voltage density of the proposed differential difference stage is performed and low noise design possibility is investigated. As an example, to show performance of differential difference stage, a modified band-pass filter with high quality factor is presented for intermediate frequency stage of FM receiver. Furthermore, the non-ideal, parasitic and stability analyses of the presented filter having high quality factor are surveyed and its working boundaries are determined.

In this study, we present two new grounded capacitance multiplier circuits based on a negative-type second-generation current conveyor (CCII-) and an inverting second-generation current conveyor (ICCII). The first proposed circuit consists of one CCII- and a voltage follower (VF) employing two NMOS transistors while the second proposed circuit is composed of an ICCII and an inverting voltage follower (IVF) including two NMOS transistors. Each circuit contains two resistors, and single grounded capacitor, which is attractive for integrated circuit realization. No active and passive component matching conditions are required for the realization of the proposed capacitance multiplier circuits. The simulation results are included to confirm the theory. (C) 2017 Elsevier GmbH. All rights reserved.

Minaei, Shahram (Dogus Author) In this paper, a new method is presented to increase the quality factor of bandpass filters employing active elements. Using the proposed method the values of the externally capacitors in filter structure are reduced. In this way chip area which is an important parameter in the integrated circuits can be minimized. Moreover, bandpass filters are investigated from the point of view of stability conditions and effects of the parasitic and non-ideal elements. Considering these effects, operating conditions and boundaries of the bandpass filter are calculated. To validate the feasibility of the method, an application example of bandpass filter used in intermediate frequency (IF) stage of AM receivers is given and the performance of the circuit is demonstrated by comparing the theory and simulation.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) NMOS based circuit realizations of a sinusoidal quadrature oscillator, a transconductance, a transimpedance amplifier are presented. All the circuits are constructed with a voltage-mode “Metamutator” consisting of an analog adder and a subtractor which is one of its possible realizations. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for adder, six for subtractor). Another significant advantage of the proposed circuits is that no external passive element is needed for the oscillator and only one resistor is used for each amplifier circuit; a variable resistor can provide gain adjustability. The post-layout simulations of all the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V power supply voltage.

In this paper a high-performance low-voltage low-power CMOS second-generation current conveyor (CCII) is presented. The proposed CCII is based on super transistor (ST) and enables low input impedance at X terminal and high output impedance at Z terminal. It also utilizes a novel power saving strategy in which a single NMOS cascode current mirror conveys X terminal current to Z terminal, provides high impedance at Z terminal and reduces the X terminal impedance all together resulting in a low-power and compact structure. As another advantage, only NMOS transistors are used in processing voltage and current signals granting the proposed CCII high frequency operation. PMOS transistors are used only for biasing. However, the proposed CCII cannot provide infinite impedance at Y terminal. HSPICE simulations using 0.18 µm parameters and supply voltage of ±0.9 V confirms that the proposed CCII exhibits impedances of 0.155 Ω, 1.6 MΩ and 47 kΩ at X, Z and Y terminals, respectively. Voltage and current bandwidths are also 377 MHz and 159 MHz, respectively. Some of the applications of the proposed CCII are given. DOI: http://dx.doi.org/10.5755/j01.eie.24.2.17948

Minaei, Shahram (Dogus Author) A novel current-mode rms-to-dc converter architecture is introduced in this paper. It is constructed from a current squaring stage and a lowpass filter with low cutoff frequency realized using the concept of Log-Domain filtering. Due to the employment of the current-splitter, two-quadrant operation capability is achieved by the converter. The Log-Domain technique offers the benefits of large-signal operation and realization of the required time-constant using a capacitor of an integrable value. Another attractive feature of the proposed scheme is its low-power operation capability originated from the employment of MOS transistors operated in the subthreshold region and its simple circuitry.

Minaei, Shahram (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2018; Florence; Italy; 27 May 2018 through 30 May 2018. Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.

Minaei, Shahram (Dogus Author) A new voltage-mode (VM) proportional integral derivative (PID) controller employing only a single active component named Current Feedback Operational Amplifier (CFOA), two resistors and two grounded capacitors is proposed. The proposed PID controller employs a canonical number of only grounded capacitors without requiring any critical passive component matching conditions and cancellation constraints. It has high input and low output impedances; thus, it can be easily cascaded with other VM structures. It can be easily constructed by a single commercially available active element. Frequency-dependent non-ideal gain and parasitic impedance effects on the performance of the proposed PID controller are investigated. The performance of the proposed PID controller circuit is demonstrated by using PSPICE circuit simulation program and an experiment. Also, 0.18 μm CMOS TSMC technology parameters with ±2 V supply voltages are used. Total power dissipation of the proposed PID controller is 1.64 mW.

In this study, two new lossless grounded inductor simulators (GISs) made up of a single plus-type second generation current conveyor, two inverting voltage buffers and a minimum number of passive components are proposed. There is no requirement of matching conditions and cancellation constraints among passive elements of the proposed GISs. Nevertheless, both of the proposed GISs have a floating capacitor which can be easily realized in nowadays integrated circuit fabrication. A second-order voltage-mode band-pass filter application is given for the proposed lossless GISs. A number of simulations based on SPICE program are given so as to verify the theory. (C) 2017 Elsevier GmbH. All rights reserved.

In this paper, a new low-power versatile current-mode rectifier is proposed. As a salient feature, the proposed rectifier provides two positive half-wave, two inverting negative half-wave or two full-wave outputs from the same configuration. The proposed circuit employs only a dual-output second-generation current conveyor (DO-CCII) and a core rectifying circuit consisting of twelve MOS transistors. The input and output signals are current. Favorably, by adding two additional transistors, the proposed rectifier can also rectify voltage signals with electronic tuning capability. The simple and MOS only structure of the proposed circuit is highly attractive from integration point of view. In spite of providing multiple outputs at the same time, the proposed rectifier enjoys low power consumption. PSPICE simulations using 0.18 mu m CMOS parameters and supply voltage of +/- 0.9 V demonstrate a precise operation and good temperature stability. (C) 2017 Elsevier GmbH. All rights reserved.

Minaei, Shahram (Dogus Author) In this paper a new topology for implementing Current-Mode Instrumentation Amplifiers (CMIA) is presented. The proposed CMIA is based on two single input-multiple output (SI-MO) current operational amplifiers (COAs) as basic building blocks and 2 resistors. To electronically control the differential mode gain, a transistor operating in triode region is used which acts as a variable resistor. The significant feature of the proposed CMIA is that the active building blocks operate in closed loop configuration. Therefore it exhibits numerous remarkable features such as improved frequency performance, low THD and very low input impedance. In addition, it has fully differential output which reduces the output noise and increases its application. The proposed CMIA is analyzed and simulated with SPICE program using parameters of 0.18 mu m CMOS technology and supply voltage of +/- 0.9 V.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push-pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 mu m process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 mu A quiescent current from a 3.3V power supply.

Actively simulated grounded inductors have been used in several applications ranging from filter to oscillator design as well as cancellation of parasitic inductances. In this paper, new grounded inductance simulators employing only one voltage differencing current conveyor (VDCC) and two passive components are proposed. Two new topologies for realizing positive and negative lossless inductances and four different topologies for realizing lossy inductances are proposed. The aim of this paper is to present new inductance simulators using the minimum number of active and passive components. The proposed inductance simulators can be tuned electronically by changing the biasing current of the VDCC. Moreover, the circuits do not require any conditions of component matching. Finally, using one of the proposed inductance simulators a third-order high-pass filter is constructed. The performance of the proposed filter is verified and simulated by using SPICE.

Minaei, Shahram (Dogus Author) In this paper, a new electronically tunable current-mode (CM) first-order universal filter as a new application for inverting second-generation current conveyors (ICCIIs) is proposed. The proposed circuit is based on two ICCII and a capacitor and does not need any resistors and critical passive component matching conditions. It has one input and multiple outputs and simultaneously realizes both inverting and non-inverting first-order low-pass, high-pass and all-pass responses from the same configuration. Employing ICCII as active building block makes possible using a single transistor in linear region as a variable resistor to control filter properties electronically. Nevertheless, the proposed CM first-order universal filter possesses a floating capacitor which can be easily realized in nowadays integrated circuit technologies. It is designed and simulated with SPICE program using 0.13 mu m IBM CMOS parameters and supply voltage of +/- 0.75 V. Non-ideal analysis and Monte Carlo simulation results are also given, which prove good enough response even in the presence of non-idealities and process parameter variations.

Minaei, Shahram (Dogus Author) The aim of this paper is proposing an alternative method to Gorski-Popiel Technique in realization of synthetic transformers. A new synthetic floating transformer (FT) circuit is also given. The proposed synthetic transformer circuit uses two current backward transconductance amplifiers (CBTAs), three resistors, and two grounded capacitors. The primary selfinductance, the secondary self-inductance, and the mutual inductance can be independently controlled and can be tuned electronically by changing the biasing current of the employed CBTAs. It has a good sensitivity performance with respect to tracking errors. A band-pass filter is also realized to test the performance of the proposed synthetic transformer circuit. The validity of the proposed synthetic transformer circuit is demonstrated by PSPICE simulations and experimental results.

Minaei, Shahram (Dogus Author) -- Conference full title: 2017 European Conference on Circuit Theory and Design (ECCTD); Catania; Italy; 4-6 September 2017. In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its input and output signals are current and it enjoys low input and high output impedances, respectively. Due to the inefficiency of the existing ECCIIs, a new ECCII circuit is also designed to be used in the proposed CMIA structure. PSPICE simulation results using 0.18μm TSMC CMOS technology and supply voltage of ±0.9V, shows CMRR of 42dB and fixed -3dB bandwidth of 68MHz for differential-mode gain ranging from 0dB to 27dB.

Minaei, Shahram (Dogus Author) -- Yıldız, Merih (Dogus Author) In this paper, a voltage-mode full-wave rectifier circuit is proposed. The proposed full-wave rectifier circuit consists of only a single negative-type second-generation current conveyor, two diodes, and two matched resistors. The proposed circuit, without requiring any external bias voltages and currents, has a simple structure using a minimum number of active and passive components. It is implemented with AMS 0.35 mu m technology operating with +/- 1.65 V. Computer simulation and experimental results are included to verify the theory. (c) 2017 Sharif University of Technology. All rights reserved.

A novel topology for realizing voltage-mode (VM) full-wave rectifier/sinusoidal frequency doubler based on current feedback operational amplifiers (CFOAs) and n-channel metal-oxide semiconductor (NMOS) transistors is proposed in this study. The proposed full-wave rectifier structure employs two CFOAs and three enhancement-mode NMOS transistors. With a slight modification, the sinusoidal frequency doubler circuit can be adopted from the full-wave rectifier circuit by replacing a grounded resistor instead of one of the NMOS transistors. Both of the proposed circuits enjoy low output and high input impedance properties which make them convenient for cascading easily with other VM circuits without needing any extra buffer circuits. No passive component matching conditions are needed. The proposed circuits are simulated by using SPICE program to verify the theoretical analysis. © 2017, Springer Science+Business Media, LLC.

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-mu m CMOS process model under supply voltage of +/- 0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Omega for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

In this letter, a new voltage-mode (VM. Configuration for providing low-power and simultaneous realization of first-order low-pass, high-pass and all-pass filters is presented. The output of the all-pass filter is taken differentially. The proposed circuit contains low number of components, i.e., only two NMOS transistors, a floating battery, a grounded capacitor and a floating resistor. Adding two NMOS transistors to the proposed circuit it is modified as an all-pass filter with a single-ended output. The main advantage of the presented circuits in comparison with other counterparts is their extremely low power dissipation. Moreover, the floating resistor can be replaced with an additional NMOS transistor in triode region to provide electronic tunability. Simulation results using SPICE program are given to demonstrate the performance of the proposed circuit. © 2011 Springer Science+Business Media, LLC.

In this paper, a new voltage-mode (VM) first-order phase shifter (all-pass filter) employing only four NMOS transistors and minimum number of passive elements (i.e. one resistor and one capacitor) is proposed. The proposed VM phase shifter has high input impedance and does not require passive element matching constraints. Moreover, since only two NMOS transistors are stacked between positive and negative supply voltages, the proposed circuit is suitable for low-voltage operation. Electronic tunability can be provided easily by replacing the employed resistor with an NMOS transistor operating in triode region. Simulation results based on 0.18 μm TSMC CMOS parameters with ±0.9 V supply voltages are given to demonstrate the performance of the proposed phase shifter. © Springer Science+Business Media, LLC 2011.

In this paper, a novel design for realizing a voltage-mode (VM) all-pass filter utilizing two differential voltage current conveyors (DVCCs) is proposed. Also, the suggested filter uses a canonical number of passive elements (one grounded capacitor and one resistor) without requiring any element matching condition. The proposed filter has high input and low output impedances, which make it suitable for cascading. The effects of the nonidealities of the DVCCs on the proposed design are investigated. As an application, a quadrature oscillator is designed using the proposed VM all-pass filter and an integrator. The proposed filter and oscillator circuits are simulated using the SPICE simulation program to confirm the theory.

In this paper two new voltage-mode (VM) universal filters employing three plus-type differential voltage current conveyors (DVCC+s) and grounded passive elements are presented. The first proposed filter is a single-input five-output (SIFO) circuit which can realize simultaneously all of the standard responses, i.e. low-pass (LP), band-pass (BP), high-pass (HP), all-pass (AP) and notch (NH) from the same configuration. The second proposed circuit is a three-input single-output (TISO) universal filter for realizing standard responses depending on the selection of the input signal from the same topology. Both of the proposed filters have the advantage of a high input impedance, which enables easy cascading to obtain higher order filters. The proposed filters are simulated using the SPICE program to verify the theoretical analysis. © Springer Science+Business Media, LLC 2009.

In this article, a universal nth-order current-mode filter employing electronically tunable second-generation current conveyors (ECCIIs) and grounded passive elements is proposed. As the current gain of the ECCII can be controlled electronically by adjusting the ratio of its DC bias currents, it is possible to tune all the coefficients of the transfer function independently. SPICE simulation results using TSMC 0.35 mu m CMOS process model are included to verify the theory. Furthermore, a design example of a fourth-order video band filter is given to illustrate the application of the introduced topology in analog circuit design.

In this paper a mixed-mode (input and output signals can be current or voltage) Kerwin-Huelsman-Newcomb (KHN) biquad with low/high input impedance and high/low output impedance depending on the type of the corresponding signal (current/voltage) is presented. The circuit is constructed using three differential voltage current conveyors (DVCCs), two grounded capacitors and three grounded resistors. The circuit simultaneously provides bandpass (BP), highpass (HP) and lowpass (LP) responses when the output is current and notch, BP and LP responses when the output is voltage. The notch and allpass responses can be obtained by connecting appropriate output currents directly without using additional active elements. Because of the low input and high output impedance of the circuit for current signals and the high input and low output impedance for voltage signals, it can be used in cascade for realizing higher-order filters. SPICE simulation results are given to verify the theoretical analysis.

In this article a dual output filter synthesis topology is proposed using a negative impedance converter (NIC) and the minimum number of passive components. Different from the preceding NIC based synthesis methods, the proposed circuits allow passive element matching to reduce the number of passive elements. The proposed dual output topology can simultaneously provide all-pass, notch/high-pass or notch/low-pass filter configurations. Also, the proposed filters have a pole frequency independent of the voltage and current gain deviations of the active element, so it is suitable for pole frequency sensitive applications. Simulations, including a post-layout simulation, Monte-Carlo analysis and Routh-Hurwitz stability tests are performed to verify the theoretical results.

Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.

In this paper, an active network simulating mutually coupled inductors employing four second-generation current controlled conveyors, five resistors, and only two grounded capacitors is presented. The primary, secondary, and mutual simulated inductances of the circuit are independent and can be electronically tuned. The proposed circuit represents a synthetic transformer and has a positive mutual inductance. As an application, the proposed transformer is used to construct a stagger-tuned filter. Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and experimental results are given to verify the theoretical analysis. © 2008 IEEE.

In this paper, using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors (FDNRs) based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed. The type of the simulators depends on the passive element selection used in the structure of the circuit without requiring critical active and passive component-matching conditions and/or cancellation constraints. In order to show the flexibility of the proposed MCFOA, a single-input three-output (SITO) voltage-mode (VM) filter, two three-input single-output (TISO) VM filters, and an SITO current-mode (CM) filter employing a single MCFOA are reported. The layout of the proposed MCFOA is also given. A number of simulations using the SPICE program and some experimental tests are performed to exhibit the performance of the introduced structures. © 2008 IEEE.

In this paper, a new first-order current-mode (CM) universal filter employing two dual output second-generation current conveyors (DO-CCIIs), one resistor and a grounded capacitor is proposed. The proposed filter has low input and high output impedances; thus, it can be easily connected with other CM circuits. It can simultaneously realize first-order low-pass (LP) and all-pass (AP) responses and can provide high-pass (HP) response with interconnection of LP and AP responses. It can be tuned electronically by replacing with dual output second-generation current controlled conveyors (DO-CCCIIs) instead of DO-CCIIs and removing the resistor. It has only a resistor but no capacitor connected in series to X terminal of DO-CCII; accordingly, it can be operated at high frequencies. Also, it does not need any critical passive component matching conditions and cancellation constraints. A number of simulation results based on SPICE program are included to exhibit performance, workability and effectiveness of the proposed filter configuration. © 2016 World Scientific Publishing Company.

In this paper, a new voltage-mode (VM) full-wave rectifier circuit employing two plus-type differential voltage–current conveyors, two grounded resistors, and two diodes is proposed. The proposed full-wave rectifier enjoys high input impedance and low output impedance; accordingly, it is suitable for direct cascading with other VM circuits without requiring additional buffers. It employs only two grounded resistors which are advantageous for integrated circuit implementations. However, it needs a single resistor-matching condition. It is simulated using SPICE program to verify the theoretical analysis. © 2016, Springer Science+Business Media New York.

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18[Formula: see text][Formula: see text]m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68[Formula: see text]k[Formula: see text], respectively. Time domain analysis shows that for an input signal of 20[Formula: see text][Formula: see text]A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only [Formula: see text].

Minaei, Shahram (Dogus Author) -- Conference full title: 2016 39th International Conference on Telecommunications and Signal Processing, TSP : June 27-29, 2016, Vienna, Austria. A New CMOS resistor based current mirror with extremely low voltage requirement at input (in the range of a few mV) and output voltage requirement of about one Vds is presented. The proposed structure combines the advantages of wide input swing, wide output swing, large output impedance, low input impedance and high linearity altogether, which make it attractive for high performance low-voltage and low power applications. Pspice simulations show a very low THD of -42.2dB from a single 0.9V supply in 0.18μm, input impedance of 239Ω, output impedance of 1.2MΩ and power dissipation of only 180μW. Interestingly, the input and output voltage requirements are only 10mV and 0.1V respectively.

In this letter, complementary metal–oxide–semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35- um TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results. IEEE Computational Intelligence Society

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) In this paper an NMOS based sinusoidal oscillator is presented. The circuit is constructed with voltage-mode (VM) NMOS-based analog adder and subtractor circuits which respectively perform V1+V2 and V1-V2 operations on the input voltages. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for the adder, six for the subtractor). Another significant advantage of the proposed circuits is that no external passive components are being used. The post-layout simulations of the proposed oscillator circuit have been executed using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: European Conference on Circuit Theory and Design, ECCTD 2015; Trondheim; Norway; 24 August 2015 through 26 August 2015 In this paper, a new RC circuit realization of voltage-mode (VM) first-order all-pass filter (APF) is presented. The proposed VM APF scheme is composed of a single grounded capacitor, three resistors with one being negative. The main advantage of the circuit is the common ground terminal between the input and the output. For proper functionality passive element matching is required and the negative resistance is implemented with Arbel-Goldminz operational transconductance amplifier. The theoretical results are verified with SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters. Institute of Electrical and Electronics Engineers Inc.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, logarithmic, divider and exponential function generator circuits. It is proposed a solution for implamentation of the analog logarithmic and exponential functions, which are not an easily accessible characteristic in CMOS technology, as well as their integration in a configurable cell. Current-mode implementation of the circuits leads to straightforward and intuitive configurations. To study the performance of the circuit, effects of channel-length modulation as well as the mismatch in the threshold voltages are thoroughly discussed. The proposed circuits are designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. MATLAB results validate the simulation results which are obtained by HSPICE.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 μm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with ±0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 μW power.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2015; Lisbon; Portugal; 24 May 2015 through 27 May 2015 In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFS) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFS as useful active filter parameter, the proposed filter employs only a floating capacitor as external passive component. The pole frequency of the proposed resistorless circuit can be tuned via mutual change of input intrinsic resistance of CFS while the filter pass-band gain by means of gain of ACA. The theoretical results are verified by SPICE simulations, where TSMC 0.18 μm level-7 SCN018 CMOS process parameters were used.

In this paper, a new simulated inductor employing two resistors, one capacitor, and only a single gain-variable third-generation current conveyor (GVCCIII) is proposed. To exhibit the performance of the proposed simulated inductor, it is used in a parallel R-L-C current-mode filter. The frequency-dependent nonideal voltage gain effects of the GVCCIII on the proposed inductor are given. The low- and high-frequency limitations of the simulated inductor are investigated in detail. The simulations performed with the SPICE program agree with the theoretical analysis. Also, the proposed circuit is tested experimentally using commercially available active devices (AD844 ICs of Analog Devices) to confirm the theory.

In this paper, a novel second-order voltage-mode filter with single input and six outputs employing inverting second-generation current conveyors (ICCIIs) is presented. This filter simultaneously realizes negative and positive gain lowpass, bandpass, and highpass filter responses, and does not require active and passive element matching. The new filter has low active and passive element sensitivities, and offers orthogonal control of the angular resonance frequency (omega(O)) and quality factor (Q).

In this paper, a new trans-impedance mode single-input-three-output (SITO) filter using opamp compensation poles is presented. The proposed circuit is composed of two internally compensated operational amplifiers (OAs) and four single-output operational transconductance amplifiers (OTAs), without using any external passive elements. The proposed multifunction filter can realize lowpass, bandpass and highpass responses simultaneously all at low output impedances. No matching condition is required. The circuit is suitable for monolithic implementation either with complementary metal oxide semiconductor (CMOS) or bipolar technologies. All of active sensitivities are low. The performance of the circuit is tested using SPICE simulation program.

In this paper, a current-mode (CM) Kerwin–Huelsman–Newcomb (KHN) biquad is proposed. The circuit employs three differential-voltage current conveyors (DVCCs) as active elements together with two capacitors and four resistors as passive elements, which all are grounded. The circuit simultaneously provides the three basic filter functions, namely bandpass (BP), highpass (HP) and lowpass (LP) functions. The notch and allpass (AP) functions can be obtained by connecting appropriate output currents directly without using additional active elements. The output signals are obtained at high output impedance ports, which is important for easy cascading in CM operation. SPICE simulation results are given to verify the theoretical analyses.

yayıncısurumuyok# ; Tam metin hakemden geçmiş kopyadır. In this paper, a new configuration suitable for realization of differential input-differential output first order, second order all-pass and notch filters with high CMRR is given. The proposed configuration uses two negative type second-generation current conveyors (CCII-), and three admittances. Two first order and one second order all-pass filters and a notch filter (tunable if current controlled conveyor CCCII is used) are extracted from the proposed configuration. Tracking error, element mismatch, sensitivity analysis, simulation and experimental results are included.

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions-all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters omega(o) and omega(o)/Q. No element matching conditions are imposed. Both its active and passive sensitivities are low.

In this paper a new trans-impedance mode multifunction filter using only active elements is presented. The proposed circuit is composed of three internally compensated operational amplifiers (OAs) and three single-output operational transconductance amplifiers (OTAs), without using any external passive elements. The proposed multifunction filter can realize lowpass, bandpass and highpass responses simultaneously. No matching condition is required. The circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performance of the circuit is tested using SPICE simulation program.