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Diamond holds promise as a potential candidate for future particle detectors owing to its remarkable electronic, mechanical, and thermal properties. However, a notable limitation is the need for a comprehensive model characterizing intrinsic diamond detectors. To address this, a specialized model integrated into the technology computer‐aided design simulation program is developed. The model's validation is accomplished through its application to the evaluation of an intrinsic diamond detector. Our investigation emphasizes three key attributes: charge carrier mobility, charge carrier lifetime, and the effective charge density within the bulk material. These attributes are carefully assessed using the transient current technique. Furthermore, our model serves as a valuable tool in the analysis of the quality of an high‐pressure high‐temperature diamond crystal and in the optimization of a diamond detector's design, exploiting the charge multiplication effect. This comprehensive methodology advances our grasp of diamond detector behavior and facilitates the development of even more sophisticated devices. [ABSTRACT FROM AUTHOR]

The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

We present a novel and numerically efficient approach to analyse the sensitivity of AC parameters to variations of traps in GaN HEMTs. The approach exploits an in-house TCAD simulator implementing the drift-diffusion model self-consistently coupled with trap rate equations, solved in dynamic conditions with the Harmonic Balance algorithm. The capability of the model is demonstrated studying the low-frequency dispersion of a 150 nm gate-length AlGaN/GaN HEMT output admittance Y DD as a function of the trap energy of Fe-induced buffer traps. The real part of Y DD exhibits strong frequency dispersion and an important degradation of the output resistance at high frequency. The imaginary part is characterized by a peak at a frequency decreasing with trap energy deeper in the gap, in agreement with experimental data on similar structures. Distributed local sources show that Y DD is most sensitive to trap energy variations localized in the buffer region under the gate, peaking under the unsaturated portion of channel towards the source. Trap variations affect the output admittance when localized in depth into the buffer up to a 100 nm distance from the channel. [ABSTRACT FROM AUTHOR]

The switching characteristics of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices of different structures were experimented after exposure to a gamma irradiation environment. The experimental results for on-state were studied. The comparisons are shown for SiC MOSFET power devices with planar, trench and double trench structures tested for total ionizing dose (TID). A higher degradation of the switching characteristics was observed for the double trench structure. The physical mechanisms for these switching characteristics variations were analyzed. In addition, they were confirmed by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

Thanks to high-current densities and cutoff frequencies, short-channel length AlGaN/GaN HEMTs are a promising technology solution for implementing RF power amplifiers in 5G front-end modules. These devices, however, might suffer from current collapse due to trapping effects, leading to compressed output power. Here, we investigate the trap dynamic response in 0.15 μm GaN HEMTs by means of pulsed I-V characterization and drain current transients (DCTs). Pulsed I-V curves reveal an almost absent gate-lag but significant current collapse when pulsing both gate and drain voltages. The thermally activated Arrhenius process (with EA ≈ 0.55 eV) observed during DCT measurements after a short trap-filling pulse (i.e., 1 μs) indicates that current collapse is induced by deep trap states associated with iron (Fe) doping present in the buffer. Interestingly, analogous DCT characterization carried out after a long trap-filling pulse (i.e., 100 s) revealed yet another process with time constants of about 1–2 s and which was approximately independent of temperature. We reproduced the experimentally observed results with two-dimensional device simulations by modeling the T-independent process as the charging of the interface between the passivation and the AlGaN barrier following electron injection from the gate. [ABSTRACT FROM AUTHOR]

A novel trench beside field limiting rings (TBFLR) terminal for 4H-SiC junction barrier Schottky (JBS) diodes is introduced and analyzed by technical computer-aided design (TCAD) simulation, addressing the electric field crowding challenge in high-voltage applications. The design parameters of the devices are optimized by striking a balance between forward and reverse electrical performances. Comparative analysis reveals that TBFLR significantly reduces the surface peak electric field, making it particularly advantageous for shallow-junction devices. Conversely, trench inside FLR (TFLR) is suited for deep-junction applications due to its deeper junction and higher breakdown voltage (BV). The TBFLR design excels with its low on-resistance and compact terminal length, especially in ultra-high voltage (>6500 V) scenarios, achieving target BV with fewer rings and reduced terminal area. Notably, the TBFLR has a terminal efficiency of at least 80 % while keeping trench depth within the 60 % range of the junction depth. Furthermore, an enhanced computational model is proposed, which introduces harmonic parameters to quantify the role of the trench in FLR, and this adaptable model can be effectively extended to the composite renewal of FLR structures. This work provides a distinct application strategy for trench-based FLR structures, significantly broadening the scope of terminal design possibilities. • Introducing novel 4H-SiC diodes with trench beside field limiting ring terminal. • Pioneering termination design mitigates challenges posed by electric field crowding. • Enhanced analytic model precisely quantifies trench impact on field limiting ring. • New termination benefits shallow junction diodes, expanding design possibilities. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate pH sensing using the out-of-equilibrium body potential (V B) monitored in silicon-on-insulator (SOI) double-gate "ISFET-like" devices with deposited metal contacts. Similar to the behavior of a dual-gate ISFET, in this study, the conductive channel induced by the back-gate voltage at the silicon/buried oxide (Si/BOX) interface is modulated by the charges to-be-sensed that are intentionally placed on the top silicon oxide layer SiO 2 covering the Si film. The detection of the surface charge modulation was evidenced by monitoring in real-time the out-of-equilibrium body potential, while the classic shift in the drain current served as control experiment and for benchmarking. These first experiments demonstrate the successful implementation of this new pH detection paradigm, with super-Nernstian sensitivity. To provide optimization options for the body-potential sensing, TCAD simulations of the pH sensors were performed in a 2D structure and illustrated the possibility to further enhance the device sensitivity with an optimized architecture. Moreover, the pH-induced shift occurs at very high applied gate biases for the drain current, contrary to the body potential, which implies a sensor with lower power consumption when V B is used as reading method. Thus, body potential monitoring provides a promising reading method to reach the required low-power consumption regime of the tomorrow's sensing devices. [Display omitted] • Out-of-equilibrium body potential, a new dynamic reading method with ISFET-like devices. • Super-Nernstian response in Silicon-On-Insulator sensors with deposited metal contacts. • Fabrication of ISFETs for "in-liquid" detection based on the out-of-equilibrium body potential. • Sensitivity investigation of ISFET sensors through TCAD simulations. • Benchmark of sensing: out-of-equilibrium body potential versus drain current method. [ABSTRACT FROM AUTHOR]

The defectiveness of InGaN-based quantum wells increases with low indium contents, due to the compressive strain induced by the lattice mismatch between the InGaN and GaN layers, and to the stronger incorporation of defects favored by the presence of indium. Such defects can limit the performance and the reliability of LEDs, since they can act as non-radiative recombination centers, and favor the degradation of neighboring semiconductor layers. To investigate the location of the layers mostly subjected to degradation, we designed a color-coded structure with two quantum wells having different indium contents. By leveraging on numerical simulations, we explained the experimental results in respect of the ratio between the emissions of the two main peaks as a function of current. In addition, to evaluate the mechanisms that limit the reliability of this type of LED, we performed a constant-current stress test at high temperature, during which we monitored the variation in the optical characteristics induced by degradation. By comparing experimental and simulated results, we found that degradation can be ascribed to an increment of traps in the active region. This process occurs in two different phases, with different rates for the two quantum wells. The first phase mainly occurs in the quantum well closer to the p-contact, due to an increment of defectiveness. Degradation follows an exponential trend, and saturates during the second phase, while the quantum well close to the n-side is still degrading, supporting the hypothesis of the presence of a diffusive front that is moving from the p-side towards the n-side. The stronger degradation could be related to a lowering of the injection efficiency, or an increment of SRH recombination driven by a recombination-enhanced defect generation process. [ABSTRACT FROM AUTHOR]

Si-based cold source field-effect transistor (CSFET) combines the benefits of sub-60-mV/dec steep-slope switching, high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ current, and compatibility with current Si CMOS process technology. Therefore, it is a promising candidate for future energy-efficient logic technology. For the first time, we present device and circuit benchmark of Si-based gate-all-around (GAA) CSFET versus conventional GAA MOSFET. The device’s characteristics are first generated using a calibrated multiscale TCAD framework. Then a novel SPICE device compact model based on neural network is created to capture the unique CSFET ${I}-{V}$ and ${C}-{V}$ data with high precision. This SPICE model further enables the circuit benchmark simulations. Through this approach, it is identified that compared with GAA MOSFET, Si-based GAA CSFET shows up to 67% performance/power gain for a supply voltage (${V}_{\text {dd}}$) below 0.43 V in an ideal gate-loaded ring oscillator circuit. It is 70% more energy-efficient in the capacitive-loaded fan-out of 4 (FO4) inverter circuit. Finally, the comparisons of GAA CSFETs with different nanosheet widths are accomplished for design technology cooptimization (DTCO) purpose. [ABSTRACT FROM AUTHOR]

Radiation-induced leakage current degradations for SiC power MOSFETs are investigated by 181Ta ion irradiation. An ion flux-related leakage degradation is reported for the first time. It is manifested as a more significant leakage current under higher flux irradiation than that under low flux irradiation, even though the total fluence is the same. Emission microscope (EMMI) results show that more leakage paths are formed for high flux irradiation. The drain bias during irradiation is another key fact to affect the radiation-induced leakage degradation. The leakage only occurs when the drain bias is larger than 300 V for flux = 1000/cm $^{2}\cdot \text{s}$ irradiation. An interesting phenomenon is that although radiation-induced leakage is not observed at 200 V with ion flux of 1000/cm $^{2}\cdot \text{s}$ , leakage appears when the ion flux increases to 6000/cm $^{2}\cdot \text{s}$. A multi-ion interaction theory is proposed to explain the above phenomenon. The mechanisms of these phenomena are also proved by TCAD simulations. [ABSTRACT FROM AUTHOR]

Negative capacitance (NC) emerges as a promising technology for low-power, high-performance transistors. The HiEnD project intends to analyze and design high-energy efficient electronic devices based on innovative ferroelectric materials. It explores NC technology for high-resolution tracking detectors in future high-energy physics experiments. It aims to create ultra-thin, radiation-resistant devices for superior signal detection in harsh environments. This paper presents detailed modeling, simulation results, and a comparison with experimental data, highlighting the potential of the developed methodology but also of the technology for the realization of compact, high-performance detectors. Advanced Technology CAD modeling has been employed to investigate the potentiality of NC devices in unconventional application domains, such as high-energy physics experiments. Numerical simulations, capable of verifying experimental results, enhance predictive power, reducing time and cost in detector design and testing. [ABSTRACT FROM AUTHOR]

To cope with the increased occupancy and radiation dose expected at the High-Luminosity LHC, the ATLAS experiment will replace its current Inner Detector with the Inner Tracker (ITk), consisting of silicon-based pixel and strip sub-detectors. The strip detector will consist of n + -in- p sensors fabricated by Hamamatsu Photonics, with 300 μ m signal-generation thickness and approximately 75 μ m strip pitch. To guide the operation of these sensors in the ITk, it is desirable to understand the basic mechanisms underlying their performance, including the effects of the radiation fluence (up to 1. 6 × 1 0 15 1-MeV n eq /cm 2) expected during operation. To this end, we have used Sentaurus TCAD to develop a 2D simulation of the ITk large-format strip sensor, based on detailed optical and electrical measurements of the sensors and of test devices fabricated on the same wafers. Current–voltage and capacitance–voltage behaviour is reproduced in the simulation by implementing charge trapping due to defects in the silicon, and the dependence of sensor behaviour on the location of these defects is investigated. Defect parameters are obtained using existing frameworks, such as the Perugia model of surface and bulk radiation damage, and through deep-level transient spectroscopy of test devices on the sensor wafers. [ABSTRACT FROM AUTHOR]

The breakdown voltage of silicon sensors is known to be affected by the ambient humidity. To understand the sensor's humidity sensitivity, Synopsys TCAD was used to simulate n-in-p sensors for different effective relative humidities. Photon emission of hot electrons was imaged with a microscope to locate breakdown in the edge-region of the sensor. The Top-Transient Current Technique was used to measure charge transport near the surface in the breakdown region of the sensor. Using the measurements and simulations, the evolution of the electric field with relative humidity and the carrier densities towards breakdown in the periphery of p-bulk silicon sensors are investigated. [ABSTRACT FROM AUTHOR]

Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with a silicon channel utilizing a sectorial cross section is evaluated in terms of Ion/Ioff current ratio, transconductance, subthreshold slope, threshold voltage roll-off, and drain induced barrier lowering (DIBL). In addition, the scaling behavior of electronic figures of merit is comprehensively studied with the aid of physical simulations. The electrical characteristic of proposed structure is compared with a circular GAA-FET, which is previously calibrated with an IBM sample at the 22 nm channel length using 3D-TCAD simulations. Our simulation results show that sectorial cross section GAA-FET is a superior structure for controlling short channel effects (SCEs) and to obtain better performance compared to conventional circular cross section counterpart.

Fully depleted monolithic active pixel sensors (FD-MAPSs) represent a state-of-the-art detector technology and profit from a low material budget and cost for high-energy physics experiments and other fields of research like medical imaging and astro-particle physics. Compared to the MAPS currently in use, fully depleted pixel sensors have the advantage of charge collection by drift, which enables a fast and uniform response overall to the pixel matrix. The functionality of these devices has been shown in previous proof-of-concept productions. In this article, we describe the optimization of the test pixel designs that will be implemented in the first engineering run of the demonstrator chip of the ARCADIA project. These optimization procedures include radiation damage models that have been employed in Technology Computer Aided Design simulations to predict the sensors’ behavior in different working environments.

Thanks to high-current densities and cutoff frequencies, short-channel length AlGaN/GaN HEMTs are a promising technology solution for implementing RF power amplifiers in 5G front-end modules. These devices, however, might suffer from current collapse due to trapping effects, leading to compressed output power. Here, we investigate the trap dynamic response in 0.15 μm GaN HEMTs by means of pulsed I-V characterization and drain current transients (DCTs). Pulsed I-V curves reveal an almost absent gate-lag but significant current collapse when pulsing both gate and drain voltages. The thermally activated Arrhenius process (with EA ≈ 0.55 eV) observed during DCT measurements after a short trap-filling pulse (i.e., 1 μs) indicates that current collapse is induced by deep trap states associated with iron (Fe) doping present in the buffer. Interestingly, analogous DCT characterization carried out after a long trap-filling pulse (i.e., 100 s) revealed yet another process with time constants of about 1–2 s and which was approximately independent of temperature. We reproduced the experimentally observed results with two-dimensional device simulations by modeling the T-independent process as the charging of the interface between the passivation and the AlGaN barrier following electron injection from the gate.

Radiation-hard photodiode structures implemented in medical applications are designed in 180-nm CMOS technology. Designed photodiodes were tested against total ionizing doses (TIDs) of 100, 200, and 400 Gy(Si), respectively, and they show high stability in terms of dark current characteristics. After TID of 400 Gy(Si), the dark current increased by up to 15%, compared to the unirradiated characteristics values. TCAD electrical simulations were performed and calibrated with the dark current measurements in order to explain the impact of generated defects due to ionizing radiation. Parameters that are used to model TID radiation have been varied in physical boundaries in order to achieve the desired fitting with the measurements. It is shown that due to the filling of acceptor interface traps with electrons, the space charge region extends, but the extension is limited and partially compensated by the fixed positive charges in the silicon nitride layer. The presented photodiodes result in the improved radiation hardness over the design in 350-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The defectiveness of InGaN-based quantum wells increases with low indium contents, due to the compressive strain induced by the lattice mismatch between the InGaN and GaN layers, and to the stronger incorporation of defects favored by the presence of indium. Such defects can limit the performance and the reliability of LEDs, since they can act as non-radiative recombination centers, and favor the degradation of neighboring semiconductor layers. To investigate the location of the layers mostly subjected to degradation, we designed a color-coded structure with two quantum wells having different indium contents. By leveraging on numerical simulations, we explained the experimental results in respect of the ratio between the emissions of the two main peaks as a function of current. In addition, to evaluate the mechanisms that limit the reliability of this type of LED, we performed a constant-current stress test at high temperature, during which we monitored the variation in the optical characteristics induced by degradation. By comparing experimental and simulated results, we found that degradation can be ascribed to an increment of traps in the active region. This process occurs in two different phases, with different rates for the two quantum wells. The first phase mainly occurs in the quantum well closer to the p-contact, due to an increment of defectiveness. Degradation follows an exponential trend, and saturates during the second phase, while the quantum well close to the n-side is still degrading, supporting the hypothesis of the presence of a diffusive front that is moving from the p-side towards the n-side. The stronger degradation could be related to a lowering of the injection efficiency, or an increment of SRH recombination driven by a recombination-enhanced defect generation process.

A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.

Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with a silicon channel utilizing a sectorial cross section is evaluated in terms of I on /I off current ratio, transconductance, subthreshold slope, threshold voltage roll-off, and drain induced barrier lowering (DIBL). In addition, the scaling behavior of electronic figures of merit is comprehensively studied with the aid of physical simulations. The electrical characteristic of proposed structure is compared with a circular GAA-FET, which is previously calibrated with an IBM sample at the 22 nm channel length using 3D-TCAD simulations. Our simulation results show that sectorial cross section GAA-FET is a superior structure for controlling short channel effects (SCEs) and to obtain better performance compared to conventional circular cross section counterpart. [ABSTRACT FROM AUTHOR]

An amorphous indium gallium zinc oxide (a‐IGZO) layer is deposited on very thin conductive amorphous indium zinc oxide (a‐IZO) thin film to demonstrate high‐performance, coplanar thin‐film transistors (TFTs) with dual‐channel oxide semiconductor architecture. Based on material properties, a conduction band offset (∆EC) of ≈0.28 eV between a‐IZO and a‐IGZO layers and a conduction band bending of ≈0.3 eV at a‐IGZO/gate insulator (GI) interface exist. Through the electrical characterization, high field‐effect mobility (μFE) of ≈50 cm2 V−1 s−1, a positive threshold voltage (VTh) of ≈2.3 V, and low off‐current (IOFF) of <1 pA in coplanar a‐IZO/a‐IGZO TFT are demonstrated. The electron accumulation (>5 × 1018 cm−3) at both the a‐IZO/a‐IGZO and a‐IGZO/GI interfaces confirm the dual‐channel conduction. The bottom a‐IZO channel significantly contributes to increasing drain current (ID) due to large electron density (≈1019 cm−3). The dual‐channel coplanar TFT with a‐IGZO/IZO provides a guideline for overcoming the trade‐off between high μFE and positive VTh control for stable enhancement mode operation with increased ID. [ABSTRACT FROM AUTHOR]

A reverse conducting (RC) insulated gate bipolar transistor (IGBT) with p-float and n-ring surrounding trench-collector is proposed. The p-floats surrounding sidewalls of trench-collectors suppress snapback and also avoid snapback when there are semiconductor/trench-collector interface charges (Qf). The n-rings surrounding the top of the trench-collectors speed up the forward recovery and ensure a high breakdown voltage. Technology computer aided design (TCAD) simulations are carried out to compare the proposed RC-IGBT and the RC-IGBT with p-poly trench-collector (PTC RC-IGBT). With Qf = 1 × 1011 cm−2, the proposed RC-IGBT is snapback-free while the PTC RC-IGBT has a snapback voltage of 4.43 V. The peak forward recovery voltage of the proposed RC-IGBT (12 V) is much lower than that of the PTC RC-IGBT (246 V). Besides, the reverse recovery charge of the two RC-IGBTs is 48% lower than that of the PiN diode. [ABSTRACT FROM AUTHOR]

In the present work, source extended multiple field plate design is implemented on β – Ga 2 O 3 MOSFET and asymmetric doping design has been adopted in the channel such that higher doping is present at the source side and lower doping is considered at the drain side to achieve superior performance for power applications. Extensive numerical simulations using TCAD Silvaco have been conducted and the optimization of various critical parameters of the proposed device, including the number and lengths of field plates and channel doping, has been undertaken to achieve superior power performance. Further, a comparison is drawn between the proposed device with (i) the device with multiple field plates at the source side and uniform channel doping, and (ii) the conventional device (without field plates and asymmetric channel doping) in terms of various critical attributes such as ON-state resistance, drain current, transconductance, breakdown voltage and power figure of merit etc. The present study demonstrates that the proposed device yields not only a remarkable improvement of 261 % in breakdown voltage and a substantial improvement in PFoM of 1120 % but also delivers higher drain current and peak transconductance when compared to the other devices under consideration. Additionally, the performance of all devices has been investigated at elevated temperatures and it has been found that the proposed device is well-suited for high-temperature applications as well since least degradation in drain current at higher temperatures is observed for the proposed device. • Source extended multiple field plates and asymmetric doping designs have been implemented on Ga 2 O 3 MOSFET. • TCAD simulations have been performed to examine various device characteristics. • An exhaustive comparison has been carried out between various device designs. • Several figure of merits have been evaluated and compared for various devices. [ABSTRACT FROM AUTHOR]

Low-Gain Avalanche Diodes (LGADs) are a class of silicon detectors that have been specifically designed for the fast detection of minimum ionizing particles (mips) in High-Energy Physics experiments. While they provide timing resolution on the order of a few tens of picoseconds, they cannot achieve high spatial resolution due to the intrinsic characteristics of their structures. Thus, active R&D is on-going to develop detectors based on LGADs to improve their spatial resolution while maintaining the timing performance of the LGADs. Such devices are, for example, AC-coupled LGADs and Deep-Junction LGADs. Another device option is the Trench-Isolated LGAD (TI LGAD), where trenches etched at the periphery of the pixels isolate them while providing a high fill-factor. In this paper we present a variation of this latter approach, demonstrating its feasibility by means of 2-dimensional TCAD simulations. [ABSTRACT FROM AUTHOR]

The paper presents the simulation studies of 10 μμm pitch microstrips on a fully depleted monolithic active CMOS technology and describes their potential to provide a new and cost-effective solution for particle tracking and timing applications. The Fully Depleted Monolithic Active Microstrip Sensors (FD-MAMS) described in this work, which are developed within the framework of the ARCADIA project, are compliant with commercial CMOS fabrication processes. A set of Technology Computer-Aided Design (TCAD) parametric simulations was performed in the perspective of an upcoming engineering production run with the aim of designing FD-MAMS, studying their electrical characteristics, and optimizing the sensor layout for enhanced performance in terms of low capacitance, fast charge collection, and low-power operation. A fine pitch of 10 μμm was chosen to provide high spatial resolution. This small pitch still allows readout electronics to be monolithically integrated in the inter-strip regions, enabling the segmentation of long strips and the implementation of distributed readout architectures. The effects of surface radiation damage expected for total ionizing doses of the order of 10 to 105 krad were also modeled in the simulations. The results of the simulations exhibit promising performance in terms of timing and low power consumption and motivate R&D efforts to further develop FD-MAMS; the results will be experimentally verified through measurements on the test structures that will be available from mid-2021.

In this paper, a charge-based analytical model for intrinsic capacitances in tunnel field-effect transistors (TFETs) is presented. The model is derived for a Si Double-Gate (DG) n-TFET whose flexibility is applicable to single-gate or p-type TFETs as well. The model is verified comparing with the TCAD simulations as well as measurements data. Considering the capacitances of fabricated Si planar p-TFETs on Ultrathin Body, some deviations between TCAD simulations, compact model and measurements are observed. Here the effect of Schottky barriers at NiSi 2 contacts are analyzed and a theory for the reason associated deviations and the unexpected behavior of intrinsic capacitances is evolved. Furthermore, a technique to include this effect in the aforementioned model is also presented. [ABSTRACT FROM AUTHOR]

This letter investigates the possibility to replace numerical TCAD device simulations with a multi-layer neural network (NN). We explore if it is possible to train the NN with the required accuracy in order to predict device characteristics of thousands of transistors without executing TCAD simulations. Here, in order to answer this question, we present a hierarchical multi-scale simulation study of a silicon junctionless nanowire field-effect transistor (JL-NWT) with a gate length of 150 nm and diameter of an Si channel of 8 nm. All device simulations are based on the drift-diffusion (DD) formalism with activated density gradient (DG) quantum corrections. For the purpose of this letter, we perform statistical numerical experiments of a set of 1380 automictically different JL-NWTs. Each device has a unique random distribution of discrete dopants (RDD) within the silicon body. From those statistical simulations, we extract important figures of merit (FoM) such as OFF-current (IOFF) and ON-current (ION), subthreshold slope (SS), and voltage threshold (VTH). Based on those statistical simulations, we train a multi-layer NN and we compare the obtained results with a general linear model (GLM). This shows the potential of using NN in the field of device modeling and simulation with a potential application to significantly reduce the computational cost. [ABSTRACT FROM AUTHOR]

This paper presents the influence of top-gate dielectric material for graphene field-effect transistor (GFET) using TCAD simulation. Apart from silicon-based dielectric that is typically used for top-gate structure, other high-dielectric constant (high-k) dielectric materials namely aluminum oxide and hafnium oxide are also involved in the analysis deliberately to improve the electrical properties of the GFET. The unique GFET current-voltage characteristics against several top-gate dielectric thicknesses are also investigated to guide the wafer fabrication engineers during the process optimization stage. The improvement to critical electrical parameters of GFET in terms of higher saturation drain current and greater on/off current ratio shows that the use of high-k dielectric material with very thin oxide layer is absolutely necessary. [ABSTRACT FROM AUTHOR]

Abstract SILICON CARBIDE (SiC) material has attracted substantial attention during the last few years as a promising candidate for making power devices for high-temperature operation and under harsh environments. In spite of the considerable progress in device performance, reliability may be a limiting factor for the introduction of SiC MOSFETs in commercial power devices. One of the major reliability concerns is the instability of the threshold voltage in MOSFETs and, similarly, of the flat-band voltage in capacitors under normal operation conditions. This instability is attributed to trapping of channel electrons in interface and bulk oxide traps. The main goal of this work is to investigate how the trapped charges at SiO2/SiC interface influence the C/V curve. In particular, by means of 2-D numerical simulations (SILVACO tools), we could isolate the two different contributions from p-type and n-type doped regions of our MOSFET and we considered both donor and acceptor traps contributions. Then, we compared the simulation results with experimental C/V curves. A good agreement between TCAD simulations and experimental measurements was obtained. So, device simulations can provide a better understanding of such defects at SiO 2 /SiC interface and we give an insight into the influence of traps, produced during device processing or caused by radiation environment, on the output characteristics of the device. [ABSTRACT FROM AUTHOR]

In this work, an analytical model for surface potential and current through a reconfigurable tunnel field effect transistor (RTFET) are proposed. While obtaining the mathematical potential model, the whole channel region is divided into three: two regions with gate electrodes and a region in between two gates. The 2D Poisson′s equation is solved in the region under the gate by appropriately selecting the boundary conditions. The current model is derived by integrating the band to band generation rate. The analytical models are validated using technology computer-aided design (TCAD) simulation and the analytical model and TCAD simulations are in good agreement. [ABSTRACT FROM AUTHOR]

Abstract The INFN CSN5 "TIMESPOT" project aims at the development and implementation of a complete integrated tracking system featuring very high precision both in space and in time for every pixel. Within this framework we are developing 3D pixel sensors optimized for timing, while retaining their usual advantages of low depletion voltage, extreme radiation hardness, and active edges. The pixel geometries are being optimized in terms of size, electrode configuration and shape. In particular, trenched electrodes are used instead of columns, so as to achieve more uniform electric and weighting field profiles. No established technology exists for 3D sensors with trenched electrodes, so we have developed and tested the necessary process steps. In this paper we report the main design and fabrication issues and selected results from TCAD simulations. Highlights • We report on 3D pixel sensors with trenched electrodes optimized for timing. • We thoroughly discussed the design and technological aspects. • We studied with TCAD the trade-off between intrinsic speed and pixel capacitance. • We demonstrated the technological feasibility of the proposed geometries. [ABSTRACT FROM AUTHOR]

Abstract In the future ATLAS Inner Tracker detector (ITk), several silicon strip modules will be biased by a single High-Voltage (HV) line, so that a switch between each strip sensor and the HV line is required to disconnect faulty sensors. Such a switch must satisfy strict requirements, such as being radiation hard, being able to sustain high voltages in the OFF state and being able to operate in a high magnetic field. At Brookhaven National Laboratory we conceived a new kind of solid-state switch that can potentially meet all the specs: it is a HV silicon vertical JFET. Before designing and fabricating the JFET, we did a study using numerical TCAD simulations that demonstrate the feasibility of fabricating the device in a standard planar technology. We report such simulations, highlighting in particular a few key parameters to which the JFET performances are most sensitive. [ABSTRACT FROM AUTHOR]

Through 3D TCAD simulations with single charge traps, we discovered a direct evidence to the mechanism of DRAM row hammer effect. It is governed by a charge pumping process, consisting of charge capture and emission under or around an aggressor wordline and subsequent carrier migration to a victim storage node. The process is highly sensitive to the location and energy level of acceptor-type traps; a single trap may enhance the row hammer effect by a factor of 60 in a 2y-nm node. Dependencies on bitline junction depth, temperature, and hammering waveform are analyzed, and the results are in good agreement with previously reported experiments. Feature size scaling is found to aggravate the row hammer effect. [ABSTRACT FROM AUTHOR]

The three-gate (TG) silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) is proposed as an innovative type of device for use in high-density and high-speed applications. The new design is expected to exhibit excellent immunity against short-channel effects (SCEs) as well as reduced leakage current. To investigate the subthreshold characteristics of the device, a physically based analytical model for the channel potential and threshold voltage is developed based on an analytical solution of the three-dimensional Poisson equation with suitable boundary conditions. Using the model, design features including important device parameters and bias condition are examined and compared with a classical SOI-MESFET. The accuracy of the model is validated by comparison of the analytical results with the results of Silvaco simulations as well as experimental data. [ABSTRACT FROM AUTHOR]

We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may be attributed to increased charge carrier density in the channel and thus reduced saturation velocity due to carrier-carrier scattering. [ABSTRACT FROM AUTHOR]

The standard technique to electrically isolate the n + implants of segmented silicon sensors fabricated on high-ohmic p -type silicon are p + -implants. Although the knowledge of the p + -implant dose and of the doping profile is highly relevant for the understanding and optimisation of sensors, this information is usually not available from the vendors, and methods to obtain it are highly welcome. The paper presents methods to obtain this information from circular MOSFETs fabricated as test structures on the same wafer as the sensors. Two circular MOSFETs, one with and one without a p + -implant under the gate, are used for this study. They were produced on Magnetic Czochralski silicon doped with ≈ 3 . 5 × 1 0 12 cm − 2 of boron and 〈 100 〉 crystal orientation. The drain–source current as function of gate voltage for different back-side voltages is measured at a drain–source voltage of 50 mV in the linear MOSFET region, and the values of threshold voltage and mobility extracted using the standard MOSFET formulae. To determine the bulk doping, the implantation dose and profile from the data, two methods are used, which give compatible results. The doping profile, which varies between 3 . 5 × 1 0 12 cm − 3 and 2 × 1 0 15 cm − 3 for the MOSFET with p + -implant, is determined down to a distance of a fraction of a μ m from the Si - SiO 2 interface. The method of extracting the doping profiles is verified using data from a TCAD simulation of the two MOSFETs. The details of the methods and of the problems encountered are discussed. [ABSTRACT FROM AUTHOR]

The voltage stability, charge-collection properties and dark current of segmented silicon sensors are influenced by the charge and potential distributions on the sensor surface, the charge distribution in the oxide and passivation layers, and by Si–SiO 2 interface states. To better understand these phenomena, measurements on test structures and sensors before and after X-ray irradiation, and TCAD simulations including surface and interface effects are performed at the Hamburg Detector Lab. The main results of these investigations and ongoing studies are presented. [ABSTRACT FROM AUTHOR]

In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI) CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution is expected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixel and the detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters and dedicated post-processing analysis are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device but also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability, the dark count rate and the photon detection probability. A comparison between the efficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flight applications. [ABSTRACT FROM AUTHOR]

Monolithic Active Pixel Sensors (MAPS) are a promising technology that provides large sensitive areas at potentially low power consumption and low material budget. The ARCADIA project is developing Fully Depleted MAPS (FD-MAPS) with an innovative sensor design, that uses a backside bias to improve charge collection efficiency and timing over a wide range of operational and environmental conditions. The ARCADIA collaboration has produced a large set of prototypes in the first two engineering runs, with the main design consisting of a 512 × 512 pixel matrix with 25 μ m pixel pitch and other smaller active sensor arrays. Test structures of pixel matrices with pixel pitches ranging from 10 to 50 μ m and total thicknesses of 50 to 200 μ m have also been included, to ease the characterization of the sensors independently from integrated electronics. We give an overview of the status of the project and then focus on the characterization of the passive pixel matrices which include Capacitance–Voltage (CV) and Current–Voltage (IV), as well as Transient Current Technique (TCT) measurements with a red and an infrared laser. We could confirm a single pixel capacitance below 5 fF for pixels with 25 μ m pitch, and a 90% charge collection of MIP-like charge depositions within 12 ns in 100 μ m active thickness. These results are complemented and supported by Technology Computer Aided Design (TCAD) simulations. [ABSTRACT FROM AUTHOR]

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off. • In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed to address the issue related to SEUs and SEMNUs. • Considering radiation hardness ability and the overall performance, RHD14 bit-cell has a better composite indicator compared to recently proposed radiation-hardened (RHM [12]) and popular (6T) SRAM bit-cell. • RHD14 bit-cell offers 6.08 % smaller read delay compared to RHM bit-cell. The static power dissipation of RHM and RHD14 bit-cells are comparable. • This indicates that the proposed bit-cell offers better hardness against radiation compared to other bit-cells without any penalty in the overall performance. [ABSTRACT FROM AUTHOR]

The "Perugia Surface and Bulk" radiation damage model is a Synopsys Sentaurus Technology CAD (TCAD) numerical model which accounts for surface and bulk damage effects induced by radiation on silicon particle detectors. In this work, the significance of the input parameters of the model, such as electron/hole cross sections and acceptor/donor introduction rates is investigated, with respect to the changes in leakage current, full depletion voltage, charge collection efficiency and the current-related damage factor α (an irradiated device's figure of merit) of a PIN diode. Different types (IV, 1/C 2 -V) of comparisons are made between simulation outputs and experimental data taken from irradiated PIN diodes. Finally, the possibility of the analytical model's validation with the examination of the Low-Gain Avalanche Detector (LGAD) case, and its general application for future silicon sensors is discussed. [ABSTRACT FROM AUTHOR]