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Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

Now a days each and every device equipped with large capacity memories in order to full fill all the needs of customers. And there are some other parameters which plays an important role in the determination of performance of the device they are power consumption and delay. In many widgets, memory is an integral part and its size also scales down as the device size is reduced. For this reason, every computerized device has low power and high speed is a prime concern. Current day scenario suggests that 6T SRAM is commonly used for the SRAM based memorydesignsas they are advantageouscompared to other cells. Low power is the major concern of today’s electronics industries where, Static as well as Dynamic power dissipation are the two key parameters that should be taken into consideration. To meet consumer needs high bandwidth and low power and high speed consuming storages are also required. This paper mainly focuses on reducing powerdissipation of Static Random Access Memory (SRAM). Power reduction and Delay reductions are the major challenge of digital Industry. A simple and advantageous configuration of a SRAM cell is by connecting two CMOS inverters back to back. This configuration has good noise immunity.

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

This paper presents the Implementation and Comparative Analysis of Double Gate Low Power Multiplexer using Dynamic Logic Styles. The main design goal for VLSI designers is to optimize power. In Conventional CMOS with single gate terminal short channel effects and leakage problems occur. This can be overcomed by moving on to new technological era i.e., Double Gate Technology. Multiplexers are used to share several input devices concluded in a single device. Multiplexer is a digital device with 2N input lines with N selection lines giving out single output. Logic styles are which to represent logical functions in different ways that to give out better device parametrically. Dynamic logic styles that are used in Conventional CMOS for optimizing power, area, delay etc. Different types of dynamic logic styles are used in this paper like Complementary CMOS (C2 MOS), DCVS Logic, Pseudo NMOS, Domino Logic, Low Power Feed through Logic. The present proposal is to implement multiplexer using both conventional & Double Gate Technology by incorporating different dynamic logic styles. The performance parameters are compared between Conventional Multiplexer and Double Gate Multiplexer which are implemented using dynamic logic styles. This gives a rich parametrical space. The Implementation and Simulation of Low Power Multiplexer using DSCH 2.6F Microwind Tool using 120nm technology.

An estimate of the lifetimes of Σ+ and Σ− hyperons, produced by the interactions of K− mesons, has been made in a nuclear emulsion stack. The best values for the Σ hyperon mean lives are obtained as τΣ+ = (0.84−0.08+0.12) · 10−10 sec and τΣ− = (1.63−0.37+0.40 · 10−10 sec. No discrepancy is found between the lifetime values estimated by the “rest-flight” and the maximum-likelihood methods. The effect of systematic and statistical errors in the energy estimation of the hyperons on the lifetime evaluation by the maximum-likelihood method has been investigated. The mass of the Σ+ hyperon has been determined from the weighted mean range 1680.9±3.9μm, of the proton in the decay mode, Σ+ → p+π0, at rest and is found to be 1189.45±0.22 MeV.