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The evolution beyond 5G towards 6G will accelerate the transformations begun by 5G to deploy new approaches to define delivery services. The network should be accessible anywhere, always-on and with the guarantee performances. This poses new challenges to the transport network that should assure available connectivity among the functions at different levels of granularity. The transport network should be so flexible to guarantee on-demand the connectivity among the processing functions that automatically will be required and, at the same time, should assure extreme performance. Optical network and Dense Wavelength Division Multiplexing technology are relevant candidates to match high bandwidth and low latency, but new challenges are required to assure the suitable cost and size for the wireless access networks. The current optical technology, suitable used in aggregation and long-haul transport network, cannot be simply downsized to be used in the access area, but novel paradigm should be considered for the optics as well. Integrated photonics seems a promising direction to realize low cost and low size optical components for the transport network. Moreover, this technology enables a certain level of remote tunability and reconfiguration of optical equipment that allow to simplify and reduce cost of installation in field and operation of the transport network. In this paper relevant optical components for transport networks are analyzed using the integrated photonics to assess the technology challenges.

5G and its evolution towards 6G is unlocking new use cases that will require the reconsideration of the existing network architectures and its operation. As the network will be required to support new service types and radio protocol splits, the traditional physical point to point connections will need to be replaced with a transport network up to the antenna site to guarantee low latency services and high bandwidth. Optical based transport is a key enabler to realize such a convergent network, where the traditional fixed infrastructure in use for mobile services and mobile infrastructure should also support enterprises services. The Software Defined Network (SDN) and Network Function Virtualization (NFV) technology plays a key role to evolve towards digitalization. It allows to simplify the creation of new services and to implement a real decoupling between the infrastructure and the network functions that run virtually, on generic processing units located everywhere in the network. Supporting automation is a key requirement that traditional optical technology is not able to meet. In this paper the reference scenarios for the access network are presented with the analysis of their requirements and the enabling optical solutions based on integrated silicon photonics.

We demonstrate foundry-fabricated O-band III-V-on-silicon discrete-mode lasers. The laser fabrication follows the back-side-on-buried-oxide laser integration process and is compatible with complex, multilayer, silicon-on-insulator based platforms. A series of devices were characterized, with the best devices producing on-chip powers of nearly 20 mW with Lorentzian linewidths below 20 kHz and a side mode suppression ratio of at least 60 dB.

We introduce a new III-V-on-Silicon (Si) heterogeneous integration platform, where the III-V material is bonded to the back of a processed Si photonic wafer. This “Back-Side-on-Buried Oxide” (BSoBOX) process is fully compatible with active, multilayer Si photonics platforms. This article describes the process flow and reports on O-band hybrid distributed feedback (DFB) lasers of various grating periods fabricated on this platform. A comprehensive set of measurements show that the quarter-wave shifted DFB lasers have comparable performance to front-side platforms. Single-mode emission with a side mode suppression ratio around 50 dB was measured between 20 $^\circ$ C – 60 $^\circ$ C. The DFB lasers had threshold currents as low as 32 mA and produced output powers in the Si waveguide from a single-end of about 15 mW at 170 mA before the devices began to mode hop. Output powers of $\sim$ 20 mW were measured before the onset of thermal roll-off and operation up to 80 $^\circ$ C was achieved. The characteristic temperatures and thermal impedance of the lasers were evaluated and future improvements are discussed.

We present a new platform integrating heterogeneous III-V/silicon gain devices at the backside of silicon-on-insulator wafers. The fabrication relies on commercial silicon photonic processes. The performances of lasers and SOAs fabricated accordingly are reported.

Scalability of silicon photonics packaging is required to support the growing demand for bandwidth in data centers and other emerging datacom and telecom applications. Connecting fiber to chip is still considered one of the main challenges of silicon photonics today due to the need for high alignment accuracy, which in turn requires expensive assembly machines and in most cases active alignment protocols. Furthermore, current fiber assembly technologies are not suitable for multiple emerging applications with large port count such as co-packaged optics. We present here the Photonic-plug technology, a unique self-aligning optical arrangement, which enables large assembly tolerance suitable for passive alignment protocols and for scalable silicon photonics port count packaging. The Photonic-plug technology accomplishes die stacking geometry with efficient wideband surface coupling as well as with grating coupler based silicon photonic chips. The combination of the Photonic-plug's large assembly tolerances and surface coupling geometry enables efficient silicon photonics wafer level testing capabilities prior to dicing. The Photonic-plug technology takes advantage from wafer level fabrication processes for planar and accurate implementing of optical elements. A library service model, called Photonic-bump, is incorporated as part of the Photonic-plug technology through silicon photonic wafer manufacturing process for complete removal of the fibers' mechanical constraints from wafer manufacturing process. The Photonic-plug takes fiber-to-chip packaging away from specialized, low throughput and expensive tools to standard, automated and high volume flip-chip packaging machines. Standardizing optical packaging through Photonic-plug methodology will affect further silicon photonics application to thrive such as photonic FPGA, optical interposers and chip-to-chip optical connectivity.

We present a fabrication flow integrating lasers at the backside of silicon-on-insulator wafers. It is expected to be compatible with integration of other material-layers and reduce the variance of lasers performance. A DFB laser fabricated accordingly exhibits a total waveguide-coupled power of 60mW at 160mA/20°C

Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonic-packaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

Providing host Application-specific integrated circuit (ASIC) (e.g., microprocessors, switches, or field-programmable gate array (FPGAs)) with terabit per second optical transmission capabilities has emerged as a new requirement in exascale cloud data centers and high-performance computing. The combination of silicon photonics (Si-Phot) and 3-D interconnecting technologies stands as a unique solution for fulfilling this need while addressing the key factors of success that are more Gb/s/cm2, less pJ/bit, and less $/Gb/s. This paper is intended to present and evaluate several Si-Phot-based solutions for providing the host ASIC with 1-Tb/s optical transceivers. Two packaging architectures are proposed, making use of 3-D interconnecting building blocks, and motivated by the need for implementing a few hundreds of high-speed electrical interconnections. Models are given for each of the 3-D building blocks, and simulation of the overall electrical signal integrity is made for the two proposed transceiver architectures. In addition, using the capability of CMOS fabrication lines for producing low-cost transceiver chips (Si-Phot integrated circuits with their electronic ICs) and 3-D chip assemblies, it is also necessary to develop high-throughput/low-cost techniques for coupling the light from the chip to the fiber. One such technique will be presented.

Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 μm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves −14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of −10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.

We report on the design, fabrication, and characterization of a reflective transmitter targeting implementation in passive optical networks (PON) with frequency division multiplexed access (FDMA). It is made up of a Silicon photonic integrated circuit (Si-PIC) comprising a reflective Mach Zehnder modulator and its flip-chipped CMOS electronic integrated circuit driver, the two ICs being interconnected by means of high density and low parasitic copper micro pillars. Several transmissions, in an FDMA PON context, are successfully demonstrated using 500 MBaud QPSK and 16-QAM modulated subcarriers, achieving bit error rate below 2.10−3. For QPSK-modulated subcarriers (respectively, 16-QAM), the available access frequency bandwidth is measured to be 1–7 GHz (respectively, 2–4 GHz) with an available loss budget of 9 dB (respectively, 5 dB). Improvements of the Si-PIC are further identified to achieve compliancy with 31 dB ODN loss.

Due to its compact size and its ability for wavelength dense multiplexing (WDM) implementation with low-insertion-loss, silicon ring resonator modulator (Si-RRM) is acknowledged to be a good candidate for off-board escape with demand for increased bandwidth densities (>1000 Gb/s/cm $^{2})$ up to 2 km (intradata centers). Passive optical network with transmission reach up to $\sim 50$ km is another application where Si-RRMs could be of great interest (WDM and NGPON2 PONs). Nevertheless, one known characteristic of the Si-RRM is its inherent phase modulation when achieving intensity modulation, which leads to a modification of the transmission properties after propagation over a few kilometers of single-mode fiber (SMF). In this letter, we propose a model for simulating chirp effects of modulated Si-RRMs, and measure the associated transmission penalties over several SMF lengths. Simulations and measurements show to be in good agreement.

We demonstrate high-bandwidth O-band Mach–Zehnder modulators with indium phosphide-on-silicon (InP-on-Si) capacitive phase shifters that are compatible with heterogeneous laser fabrication processes. An electro-optic conversion efficiency of 1.3 V⋅cm and a 3 dB bandwidth of up to 30 GHz was observed for a phase modulator length of 250 μm at a 0 V bias. Open eye patterns were observed at up to 25 Gb/s.

We demonstrate the first backside-processed hybrid silicon discrete mode laser. It operates in the O-band with a total waveguide-coupled output power >43 mW, 850 kHz linewidth, and a side mode suppression ratio of 60 dB.

International audience; Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5V pp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm 2 per microring.

A hybrid III-V/silicon semiconductor optical amplifier (SOA) is presented, which shows a maximum fiber-to-fiber gain of 10 dB and a maximum internal gain around 28 ± 2 dB. The device was fabricated from III-V material wafer-bonded onto a silicon-on-insulator wafer. The optical mode transfers between silicon and III-V waveguides by means of waveguide tapers. Vertical grating couplers are used to connect the SOA to optical fibers. The device was packaged and tested in a transmission experiment. In a loop configuration containing 25 km of single-mode fiber, the SOA amplifies data signals of various modulation formats. Transmission with a bit error rate below the forward error correction limit is demonstrated for up to ten loops using QPSK, six loop using 8QAM, and four loops using 16QAM.

Achieving high data speed (typically Nx25 Gbps) compact optoelectronic modules is now made possible by using Photonic Integrated Circuits (PIC) combined with CMOS electronic drivers. Among the techniques that can be used to combine both circuits, flip-chip assembly based on micro-bumps shows several advantages, for example low RF parasitics and high density compared to wire bonding. Using this technique, it is possible to build low consumption photonic receivers working at 25 Gbps.

In this letter, we report about design, fabrication, and testing of echelle grating (EG) demultiplexers in the O-band (1.31- $\mu $ m) for silicon-based photonic integrated circuits. In detail, flat band perfectly chirped EGs and two-point stigmatic EGs on the 300-nm thick silicon-on-insulator platform designed for $4\times 800$ -GHz spaced wavelength-division multiplexing featuring a low average crosstalk (−30 dB), a precise channel spacing, optimized interchannel uniformity (0.7 dB) and insertion losses (3–3.5 dB) are presented. Wafer-level statistical performance analysis shows the EG spectral response to be stable over the wafer in terms of crosstalk, channel spacing, and bandwidth with minimal wavelength dispersion (

International audience; Silicon nitride-on-silicon bi-layer grating couplers were designed for the O-band using an optimization-based procedure that accounted for design rules and fabricated on a 200 mm wafer. The designs were sufficiently robust to fabrication variations to function well across the wafer. A peak fiber-to-chip coupling efficiency to standard single mode fiber of -2.2 dB and a 1-dB bandwidth of 72.9 nm was achieved in the representative device. Over several chips across the wafer, we measured a median peak coupling efficiency of -2.1 dB and median 1-dB bandwidth of 70.8 nm. The measurements had good correspondence with simulation.

International audience; Polarization-insensitive silicon nitride (SiN) 4-channel wavelength (de)multiplexers based on Mach-Zehnder interferometer lattice filters for coarse wavelength division multiplexing (CWDM) in the O-band are demonstrated in a SiN-on-silicon photonic platform. For the bestperforming device, the insertion loss was < 2.8 dB, the inter-channel crosstalk was < -11.5 dB for a polarization scrambled input, and the passband shift between the orthogonal polarizations was < 1.5 nm. Across the 200mm wafer, the die-averaged insertion loss and maximum crosstalk were 3.1 dB and -10.6 dB, respectively. The higher-than-expected crosstalk was due to dimensional variations. This work shows the potential of SiN photonic circuits forCWDMwithout polarization diversity.

The field of silicon photonics is attracting a lot of attention due to the prospect of low-cost and compact circuits that integrate photonic and microelectronic elements on a single chip. Such silicon chips have applications in optical transmitter and receiver circuits for short-distance communications as well as for long-haul optical transmissions. Silicon photonics has proven to be a successful platform for many functional elements such as low-loss waveguides, filters, multiplexers/demultiplexers, optical modulators and Ge-on-Si photodiodes. On-going developments for advanced photonic integrated circuits include compact and energy-efficient silicon modulators, temperature-insensitive passive devices and hybrid III-V on Silicon lasers. The European COSMICC project gathers key industrial and research partners in the field of silicon photonics, CMOS electronics, printed circuit board packaging, optical transceivers and datacenters, aiming at developing low-cost and low-energy consumption 50 Gb/s 4-wavelength coarse wavelength division multiplexing optical transceivers that will be packaged on-board. Combining CMOS electronics and Si-photonics with innovative high-throughput fiber attachment techniques, the developed solutions will be scalable beyond 1 Tb/s to meet the future data-transmission requirements in data-centers and super computing systems.

This paper summarizes recent advances of integrated hybrid InP/SOI lasers and transmitters based on wafer bonding. At first the integration process of III-V materials on silicon is described. Then the paper reports on the results of single wavelength distributed Bragg reflector lasers with Bragg gratings etched on silicon waveguides. We then demonstrate that, thanks to the high-quality silicon bend waveguides, hybrid III-V/Si lasers with two integrated intra-cavity ring resonators can achieve a wide thermal tuning range, exceeding the C band, with a side mode suppression ratio higher than 40 dB. Moreover, a compact array waveguide grating on silicon is integrated with a hybrid III-V/Si gain section, creating a wavelength-selectable laser source with 5 wavelength channels spaced by 400 GHz. We further demonstrate an integrated transmitter with combined silicon modulators and tunable hybrid III-V/Si lasers. The integrated transmitter exhibits 9 nm wavelength tunability by heating an intra-cavity ring resonator, high extinction ratio from 6 to 10 dB, and excellent bit-error-rate performance at 10 Gb/s.

The large internet companies' investments indicate an ongoing increase of data-based business volume through the next decades with the rise of the internet of things and the continuous growth of communication and data facilities. The two-figure yearly growth rate of exchanged data volume within data centers is challenging the actual short distance communication paradigms. With datacenter architectures getting larger and “flatter”, the availability of high bandwidth, low power and low cost optical links ranging from less than 1 meter to 1 kilometer is a key issue. It is therefore expected that today's 10 Gb/s transceiver data rate soon increase to 28Gb/s, 40 Gb/s and beyond. For such a channel bandwidth, the copper-based wires are no longer suitable in terms of cost, power and bandwidth density. Optical interconnects are expected to replace copper for short distances below 500 m and down to 1 m within servers and between servers of the same data center. They exhibit much higher scalability and flexibility in terms of bandwidth, reach and lower energy consumption down to 1 pJ/b and below. The integration of optical transceivers close to the computational logic is therefore becoming more and more attractive. The enabling technology for optical interconnect is silicon photonics which is maturing and leveraging the well-established knowledge coming from silicon technology. We today have a complete set of silicon photonics technology modules that cover passive components including multiplexers/demultiplexers, coupling functions, photodetectors, modulators and integrated laser sources. Given the constraints coming from the supply chain, we consider a heterogeneous integration of the photonics (PIC) and the electrical integrated circuits (EIC) within a single package, differentiating from a co-integration of both of them on a single die demonstrated in the past, which is not a viable nor scalable option from the economical point of view. Thereby we leverage our expertise in the 3D integration field, and we use a full set of mature technology modules including through-silicon vias (TSV), wafer thinning and micro-bumping. These modules have only been used in the past within electrical circuits, but their implantation in photonics chips has no showstoppers. The 3D integration enables a stacking of the electrical drivers in the EIC die on top of the photodiodes and modulators in the PIC die. The small micro-bump size reduces the parasitic capacitances and enables an optimized electro-optical co-design. The TSV enable the connection of the stack with the rest of the package and to the second-level interconnect with low inductive losses, thus boosting the system performance. The advanced 3D packaging technique also enables the alignment and attachment of the optical fibers using silicon micro-ferrules. Today's active alignment techniques for optical coupling are time-consuming and expensive, and not compatible with usual micro-electronics techniques. The ongoing development of silicon micro-ferrules with mechanical micro-bumps enables a compatible assembly of the optical plugs with the remaining system and a quick assembly process with standard pick-and-place equipment. The paper will introduce today's system demand in the data base market and its translation into technology requirements. It will then survey our silicon photonics technology modules and actual demonstrations. We will then introduce the packaging constraints and the impact of 3D integration on the system assembly. Finally, we will present our advances in terms of packaging of optical micro-connectors.

This letter reports a cost-effective transmitter solution for future generations of long reach passive optical networks (PONs). It is based on the direct adaptive orthogonal frequency division multiplexing modulation of a hybrid III/V-on-silicon laser. Because of low-noise and good linearity of the hybrid laser, modulation formats as high as 32-quadrature amplitude modulation are achieved. Data-rates of 21.5 and 12.4 Gb/s are demonstrated, respectively, in optical back-to-back and 50 km single-mode fiber (SMF)-link free from amplifiers, while on-off keying transmission is limited to at 20 km SMF. The proposed solution stands as a cost-effective solution for next-generation time and wavelength division multiplexing PONs with extended reach, as the hybrid laser can further be made tunable.

International audience; We report about the final results of the FABULOUS European project, demonstrating the feasibility of real-time Ethernet transmission on a self-coherent reflective passive optical network, using an optical network unit (ONU) whose main optical functions are performed by a silicon-photonics device; 500 Mbps per user with a power budget of 24 dB in offline processing and 21 dB in real time is shown. We also report details about the packaging process and the special technique developed for the flip-chipping of a CMOS electrical driver, used for driving the ONU with low voltage, onto a silicon Mach-Zehnder modulator.

Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

PAM-4 transmission is established by modulating two silicon ring modulators in series with two uncorrelated NRZ encoded data sources. The two modulators are thermally tuned to obtain different extinction ratios. 30Gb/s PAM-4 transmissions are achieved with only 1Vpp.

Growing demand for bandwidth in Datacom optical links and High Performance Computers (HPC) has recently led to new optoelectronic modules based on Silicon Photonics Integrated Circuits [1]. One of the intrinsic capabilities of this technology is its scalability in terms of aggregated data rate, due to the possibility of combining Space Division Multiplexing, Wavelength Division Multiplexing, and the use of advanced modulation formats such as PAM4 or QPSK [2]. As a result, standard commercial modules using Silicon Photonics Integrated Circuits (Si-PIC), typically providing 10 to 25 Gbps (OOK) per channel over several singlemode fibers, will evolve up to and beyond 400 Gbps and more aggregated data rate in the coming years. In this paper, we demonstrate the introduction of Wavelength Division Multiplexing in a multichannel photoreceiver module using a Si-PIC, at a data rate of 25 Gbps per channel.

Packaging of finished III-V-chips (SOAs and DFB Lasers) is the strategy adopted for providing Si-Photonic-transceivers with a laser source. With the capability for increased integration and reduced cost, where does heterogeneous-integration stand?